IDELAYCTRL - 2023.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-05-17
Version
2023.1 English

Primitive: IDELAYE2/ODELAYE2 Tap Delay Value Control

Introduction

At least one of these design elements must be instantiated when using IDELAYE2 or ODELAYE2. The IDELAYCTRL module provides a reference clock input that allows internal circuitry to derive a voltage bias, independent of PVT (process, voltage, and temperature) variations, to define precise delay tap values for the associated IDELAYE2 and ODELAYE2 components. Use the IODELAY_GROUP attribute when instantiating this component to distinguish which IDELAYCTRL is associated with which IDELAYE2 and ODELAYE2.

Port Descriptions

Port Direction Width Function
RDY Output 1 The ready (RDY) signal indicates when the IDELAYE2 and ODELAYE2 modules in the specific region are calibrated. The RDY signal is deasserted if REFCLK is held High or Low for one clock period or more. If RDY is deasserted Low, the IDELAYCTRL module must be reset. If not needed, RDY to be unconnected/ignored.
REFCLK Input 1 Time reference to IDELAYCTRL to calibrate all IDELAYE2 and ODELAYE2 modules in the same region. REFCLK can be supplied directly from a user-supplied source or the MMCME2/PLLE2 and must be routed on a global clock buffer.
RST Input 1 Active-High asynchronous reset. To ensure proper IDELAYE2 and ODELAYE2 operation, IDELAYCTRL must be reset after configuration and the REFCLK signal is stable. A reset pulse width Tidelayctrl_rpw is required.

RST (Module reset) Resets the IDELAYCTRL circuitry. The RST signal is an active-High asynchronous reset. To reset the IDELAYCTRL, assert it High for at least 50 ns.

REFCLK (Reference Clock) Provides a voltage bias, independent of process, voltage, and temperature variations, to the tap-delay lines in the IOBs. The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.

RDY (Ready Output) Indicates the validity of the reference clock input, REFCLK. When REFCLK disappears (i.e., REFCLK is held High or Low for one clock period or more), the RDY signal is deasserted.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
--             7 Series
-- Xilinx HDL Language Template, version 2023.1

IDELAYCTRL_inst : IDELAYCTRL
port map (
   RDY => RDY,       -- 1-bit output: Ready output
   REFCLK => REFCLK, -- 1-bit input: Reference clock input
   RST => RST        -- 1-bit input: Active high reset input
);

-- End of IDELAYCTRL_inst instantiation

Verilog Instantiation Template


// IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
//             7 Series
// Xilinx HDL Language Template, version 2023.1

(* IODELAY_GROUP = <iodelay_group_name> *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL

IDELAYCTRL IDELAYCTRL_inst (
   .RDY(RDY),       // 1-bit output: Ready output
   .REFCLK(REFCLK), // 1-bit input: Reference clock input
   .RST(RST)        // 1-bit input: Active high reset input
);

// End of IDELAYCTRL_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)