IOBUF_DCIEN - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: Bi-Directional Single-ended Buffer with DCI and Input Disable

Introduction

This design element is a bidirectional single ended I/O buffer used to connect internal logic to an external bidirectional pin. This element includes Digitally Controlled Impedance (DCI) termination enable/disable as well as input path disable as additional power saving features when the I/O is either in an unused state or being used as an output for a sustained amount of time. This element may only be placed in High Performance (HP) banks in the 7 series devices.

Port Descriptions

Port Direction Width Function
IO In/out 1 Bi-directional port connection. Connect directly to top-level port in the design.
I Input 1 Buffer input representing the output path to the device.
IBUFDISABLE Input 1 Disables input path. When this signal is asserted HIGH and the attribute USE_IBUFDISABLE is set to "TRUE", the input path through the input buffer is disabled and forced to a logic HIGH. If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions.
DCITERMDISABLE Input 1 Disables DCI termination. When this signal is asserted HIGH, DCI termination is disabled. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions.
T Input 1 Sets the I/O in a high impedance 3-state mode when the I/O is being used for a read (input) operation. The T pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE".
O Output 1 Buffer output representing the input path to the device.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DRIVE INTEGER 2, 4, 6, 8, 12, 16, 24 12 Selects output drive strength (mA) for the SelectIO™ buffers.
IBUF_LOW_PWR STRING "TRUE", "FALSE" "TRUE" Allows a trade off of lower power consumption vs. highest performance.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
SLEW STRING "SLOW", "FAST", "SLOW" Sets the output rise and fall time. See the Data Sheet for recommendations of the best setting for this attribute.
USE_IBUFDISABLE STRING "TRUE", "FALSE" "TRUE" Enables or disables the feature of IBUFDISABLE. Set to FALSE when it is not desirable to have the T pin disable input path to allow a read during write operation. When set to TRUE deasserting T (IO used as output) or asserting IBUFDISABLE will disable the input path through the buffer and forces to a logic high.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
--              and Input path enable/disable
--              May only be placed in High Performance (HP) Banks
--              7 Series
-- Xilinx HDL Language Template, version 2023.2

IOBUF_DCIEN_inst : IOBUF_DCIEN
generic map (
   DRIVE => 12,
   IOSTANDARD => "DEFAULT",
   IBUF_LOW_PWR => "TRUE",
   SLEW => "SLOW")
port map (
   O => O,     -- Buffer output
   IO => IO,   -- Buffer inout port (connect directly to top-level port)
   DCITERMDISABLE => DCITERMDISABLE, -- DCI Termination enable input
   I => I,     -- Buffer input
   IBUFDISABLE => IBUFDISABLE, -- Input disable input, high=disable
   T => T      -- 3-state enable input, high=input, low=output
);

-- End of IOBUF_DCIEN_inst instantiation

Verilog Instantiation Template


// IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
//              and Input path enable/disable
//              May only be placed in High Performance (HP) Banks
//              7 Series
// Xilinx HDL Language Template, version 2023.2

IOBUF_DCIEN #(
   .DRIVE(12), // Specify the output drive strength
   .IBUF_LOW_PWR("TRUE"),  // Low Power - "TRUE", High Performance = "FALSE"
   .IOSTANDARD("DEFAULT"), // Specify the I/O standard
   .SLEW("SLOW"),          // Specify the output slew rate
   .USE_IBUFDISABLE("TRUE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
) IOBUF_DCIEN_inst (
   .O(O),     // Buffer output
   .IO(IO),   // Buffer inout port (connect directly to top-level port)
   .DCITERMDISABLE(DCITERMDISABLE), // DCI Termination enable input
   .I(I),     // Buffer input
   .IBUFDISABLE(IBUFDISABLE), // Input disable input, high=disable
   .T(T)      // 3-state enable input, high=input, low=output
);

// End of IOBUF_DCIEN_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)