ISERDESE2 - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: Input SERial/DESerializer with Bitslip

Introduction

The ISERDESE2 in 7 series FPGAs is a dedicated serial-to-parallel converter with specific clocking and logic features designed to facilitate the implementation of high-speed source-synchronous applications. The ISERDESE2 avoids the additional timing complexities encountered when designing deserializers in the FPGA fabric. ISERDESE2 features include:

  • Dedicated Deserializer/Serial-to-Parallel Converter, which enables high-speed data transfer without requiring the FPGA fabric to match the input data frequency. This converter supports both single data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel converter creates a 2-, 3-, 4-, 5-, 6-, 7-, or 8-bit wide parallel word. In DDR mode, the serial-to-parallel converter creates a 4-, 6-, 8-, 10-, or 14-bit-wide parallel word.
  • Bitslip Submodule, which lets designers reorder the sequence of the parallel data stream going into the FPGA fabric. This can be used for training source-synchronous interfaces that include a training pattern.
  • Dedicated Support for Strobe-based Memory Interfaces, including the OCLK input pin, to handle the strobe-to-FPGA clock domain crossover entirely within the ISERDESE2 block. This allows for higher performance and a simplified implementation.
  • Dedicated Support for Networking Interfaces
  • Dedicated Support for Memory Interfaces

Port Descriptions

Port Direction Width Function
BITSLIP Input 1 The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted (active-High). Subsequently, the data seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one position every time Bitslip is invoked (DDR operation is different from SDR).
CE1, CE2 Input 1 Each ISERDESE2 block contains an input clock enable module.
  • When NUM_CE = 1, the CE2 input is not used, and the CE1 input is an active-High clock enable connected directly to the input registers in the ISERDESE2.
  • When NUM_CE = 2, the CE1 and CE2 inputs are both used, with CE1 enabling the ISERDESE2 for half of a CLKDIV cycle, and CE2 enabling the ISERDESE2 for the other half. The clock enable module functions as a 2:1 serial-to-parallel converter, clocked by CLKDIV. The clock enable module is needed specifically for bidirectional memory interfaces when ISERDESE2 is configured for 1:4 deserialization in DDR mode.
  • When the attribute NUM_CE = 2, the clock enable module is enabled and both CE1 and CE2 ports are available.
  • When NUM_CE = 1, only CE1 is available and functions as a regular clock enable.
CLK Input 1 The high-speed clock input (CLK) is used to clock in the input serial data stream.
CLKB Input 1 The high-speed secondary clock input (CLKB) is used to clock in the input serial data stream. In any mode other than "MEMORY_QDR", connect CLKB to an inverted version of CLK. In "MEMORY_QDR" mode CLKB should be connected to a unique, phase shifted clock.
CLKDIV Input 1 The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the width of the implemented deserialization). It drives the output of the serial-to-parallel converter, the Bitslip submodule, and the CE module.
CLKDIVP Input 1 Only supported in MIG. Sourced by PHASER_IN divided CLK in MEMORY_DDR3 mode. All other modes connect to ground.
D Input 1 The serial input data port (D) is the serial (high-speed) data input port of the ISERDESE2. This port works in conjunction only with the 7 series FPGA I/O resource.
DDLY Input 1 The serial input data port (DDLY) is the serial (high-speed) data input port of the ISERDESE2. This port works in conjunction only with the 7 series FPGA IDELAYE2 resource.
DYNCLKDIVSEL Input 1 Dynamically select CLKDIV inversion.
DYNCLKSEL Input 1 Dynamically select CLK and CLKB inversion.
O Output 1 The combinatorial output port (O) is an unregistered output of the ISERDESE2 module. This output can come directly from the data input (D), or from the data input (DDLY) via the IDELAYE2.
OCLK Input 1 The OCLK clock input synchronizes data transfer in strobe-based memory interfaces. The OCLK clock is only used when INTERFACE_TYPE is set to "MEMORY". The OCLK clock input is used to transfer strobe-based memory data onto a free-running clock domain. OCLK is a free-running FPGA clock at the same frequency as the strobe on the CLK input. The timing of the domain transfer is set by the user by adjusting the delay of the strobe signal to the CLK input (e.g., using IDELAY). Examples of setting the timing of this domain transfer are given in the Memory Interface Generator (MIG). When INTERFACE_TYPE is "NETWORKING", this port is unused and should be connected to GND.
OCLKB Input 1 The OCLK clock input synchronizes data transfer in strobe-based memory interfaces. The OCLKB clock is only used when INTERFACE_TYPE is set to "MEMORY".
OFB Input 1 The serial input data port (OFB) is the serial (high-speed) data input port of the ISERDESE2. This port works in conjunction only with the 7 series FPGA OSERDESE2 port OFB.
Q1 - Q8 Output 1 The output ports Q1 to Q8 are the registered outputs of the ISERDESE2 module. One ISERDESE2 block can support up to eight bits (i.e., a 1:8 deserialization). Bit widths greater than eight (up to 14) can be supported using Width Expansion. The first data bit received appears on the highest order Q output. The bit ordering at the input of an OSERDESE2 is the opposite of the bit ordering at the output of an ISERDESE2 block. For example, the least significant bit A of the word FEDCBA is placed at the D1 input of an OSERDESE2, but the same bit A emerges from the ISERDESE2 block at the Q8 output. In other words, D1 is the least significant input to the OSERDESE2, while Q8 is the least significant output of the ISERDESE2 block. When width expansion is used, D1 of the master OSERDESE2 is the least significant input, while Q7 of the slave ISERDESE2 block is the least significant output.
RST Input 1 The reset input causes the outputs of all data flip-flops in the CLK and CLKDIV domains to be driven low asynchronously. ISERDESE2 circuits running in the CLK domain where timing is critical use an internal, dedicated circuit to retime the RST input to produce a reset signal synchronous to the CLK domain. Similarly, there is a dedicated circuit to retime the RST input to produce a reset signal synchronous to the CLKDIV domain. Because the ISERDESE2 is driven into reset asynchronously but comes out of reset synchronously it must be treated as a synchronous reset to the CLKDIV time domain and have a minimum pulse of one CLKDIV cycle. When building an interface consisting of multiple ISERDESE2 ports, all ISERDESE2 ports in the interface must be synchronized. The internal retiming of the RST input is designed so that all ISERDESE2 blocks that receive the same reset pulse come out of reset synchronized with one another.
SHIFTIN1, SHIFTIN2 Input 1 If SERDES_MODE="SLAVE", connect SHIFTIN1/2 to the master ISERDESE2 SHIFTOUT1/2 outputs. Otherwise, leave SHIFTOUT1/2 unconnected and/or SHIFTIN1/2 grounded.
SHIFTOUT1, SHIFTOUT2 Output 1 If SERDES_MODE="MASTER" and two ISERDESE2s are to be cascaded, connect SHIFTOUT1/2 to the slave ISERDESE2 SHIFTIN1/2 inputs.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DATA_RATE STRING "DDR", "SDR" "DDR" The DATA_RATE attribute defines whether the incoming data stream is processed as single data rate (SDR) or double data rate (DDR).
DATA_WIDTH DECIMAL 4, 2, 3, 5, 6, 7, 8, 10, 14 4 Defines the width of the serial-to-parallel converter. The legal value depends on the DATA_RATE attribute (SDR or DDR).
  • If DATA_RATE = DDR, value is limited to 4, 6, 8, 10 or 14.
  • If DATA_RATE = SDR, value is limited to 2, 3, 4, 5, 6, 7, or 8.
DYN_CLKDIV_INV _EN STRING "FALSE", "TRUE" "FALSE" Enables DYNCLKDIVINVSEL inversion when “TRUE” and disables HDL inversions on CLKDIV pin.
DYN_CLK_INV_EN STRING "FALSE", "TRUE" "FALSE" Enables DYNCLKINVSEL inversion when “TRUE” and disables HDL inversions on CLK and CLKB pins.
INIT_Q1, INIT_Q2, INIT_Q3, INIT_Q4 BINARY 1'b0 to 1'b1 1'b0 Specifies the initial value on the Q1 through Q4 outputs after configuration.
INTERFACE_TYPE STRING "MEMORY", "MEMORY_DDR3", "MEMORY_QDR", "NETWORKING", "OVERSAMPLE" "MEMORY" Specifies the mode of operation for the ISERDESE2. For details on each mode, please refer to the 7 series FPGA SelectIO Resources User Guide.
IOBDELAY STRING "NONE", "BOTH", "IBUF", "IFD" "NONE" Specifies the input sources for the ISERDESE2 module. The D and DDLY pins are dedicated inputs to the ISERDESE2. The D input is a direct connection to the I/O. The DDLY pin is a direct connection to the IODELAYE2. This allows the user to either have a delayed or non-delayed version of the input to the registered (Q1- Q6) or combinatorial path (O) output. The attribute IOBDELAY determines the input applied the output.
  • "NONE": O => D | Q1-Q6 => D
  • "IBUF": O => DDLY | Q1-Q6 => D
  • "IFD": O => D | Q1-Q6 => DDLY
  • "BOTH": O => DDLY | Q1-Q6 => DDLY
NUM_CE DECIMAL 2, 1 2 The NUM_CE attribute defines the number of clock enables (CE1 and CE2) used.
OFB_USED STRING "FALSE", "TRUE" "FALSE" Enables the path from the OLOGIC, OSERDESE2 OFB pin to the ISERDESE2 OFB pin. Disables the use of the D input pin.
SERDES_MODE STRING "MASTER", "SLAVE" "MASTER" Specifies whether the ISERDESE2 module is a master or slave when using width expansion. Set to "MASTER" when not using width expansion.
SRVAL_Q1, SRVAL_Q2, SRVAL_Q3, SRVAL_Q4 BINARY 1'b0 to 1'b1 1'b0 Specifies the value (set or reset) of Q1 through Q4 outputs when the SR pin is invoked.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- ISERDESE2: Input SERial/DESerializer with Bitslip
--            7 Series
-- Xilinx HDL Language Template, version 2023.2

ISERDESE2_inst : ISERDESE2
generic map (
   DATA_RATE => "DDR",           -- DDR, SDR
   DATA_WIDTH => 4,              -- Parallel data width (2-8,10,14)
   DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
   DYN_CLK_INV_EN => "FALSE",    -- Enable DYNCLKINVSEL inversion (FALSE, TRUE)
   -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
   INIT_Q1 => '0',
   INIT_Q2 => '0',
   INIT_Q3 => '0',
   INIT_Q4 => '0',
   INTERFACE_TYPE => "MEMORY",   -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
   IOBDELAY => "NONE",           -- NONE, BOTH, IBUF, IFD
   NUM_CE => 2,                  -- Number of clock enables (1,2)
   OFB_USED => "FALSE",          -- Select OFB path (FALSE, TRUE)
   SERDES_MODE => "MASTER",      -- MASTER, SLAVE
   -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
   SRVAL_Q1 => '0',
   SRVAL_Q2 => '0',
   SRVAL_Q3 => '0',
   SRVAL_Q4 => '0'
)
port map (
   O => O,                       -- 1-bit output: Combinatorial output
   -- Q1 - Q8: 1-bit (each) output: Registered data outputs
   Q1 => Q1,
   Q2 => Q2,
   Q3 => Q3,
   Q4 => Q4,
   Q5 => Q5,
   Q6 => Q6,
   Q7 => Q7,
   Q8 => Q8,
   -- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
   SHIFTOUT1 => SHIFTOUT1,
   SHIFTOUT2 => SHIFTOUT2,
   BITSLIP => BITSLIP,           -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
                                 -- CLKDIV when asserted (active High). Subsequently, the data seen on the
                                 -- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one
                                 -- position every time Bitslip is invoked (DDR operation is different from
                                 -- SDR).

   -- CE1, CE2: 1-bit (each) input: Data register clock enable inputs
   CE1 => CE1,
   CE2 => CE2,
   CLKDIVP => CLKDIVP,           -- 1-bit input: TBD
   -- Clocks: 1-bit (each) input: ISERDESE2 clock input ports
   CLK => CLK,                   -- 1-bit input: High-speed clock
   CLKB => CLKB,                 -- 1-bit input: High-speed secondary clock
   CLKDIV => CLKDIV,             -- 1-bit input: Divided clock
   OCLK => OCLK,                 -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
   -- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
   DYNCLKDIVSEL => DYNCLKDIVSEL, -- 1-bit input: Dynamic CLKDIV inversion
   DYNCLKSEL => DYNCLKSEL,       -- 1-bit input: Dynamic CLK/CLKB inversion
   -- Input Data: 1-bit (each) input: ISERDESE2 data input ports
   D => D,                       -- 1-bit input: Data input
   DDLY => DDLY,                 -- 1-bit input: Serial data from IDELAYE2
   OFB => OFB,                   -- 1-bit input: Data feedback from OSERDESE2
   OCLKB => OCLKB,               -- 1-bit input: High speed negative edge output clock
   RST => RST,                   -- 1-bit input: Active high asynchronous reset
   -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
   SHIFTIN1 => SHIFTIN1,
   SHIFTIN2 => SHIFTIN2
);

-- End of ISERDESE2_inst instantiation

Verilog Instantiation Template


// ISERDESE2: Input SERial/DESerializer with Bitslip
//            7 Series
// Xilinx HDL Language Template, version 2023.2

ISERDESE2 #(
   .DATA_RATE("DDR"),           // DDR, SDR
   .DATA_WIDTH(4),              // Parallel data width (2-8,10,14)
   .DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
   .DYN_CLK_INV_EN("FALSE"),    // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
   // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
   .INIT_Q1(1'b0),
   .INIT_Q2(1'b0),
   .INIT_Q3(1'b0),
   .INIT_Q4(1'b0),
   .INTERFACE_TYPE("MEMORY"),   // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
   .IOBDELAY("NONE"),           // NONE, BOTH, IBUF, IFD
   .NUM_CE(2),                  // Number of clock enables (1,2)
   .OFB_USED("FALSE"),          // Select OFB path (FALSE, TRUE)
   .SERDES_MODE("MASTER"),      // MASTER, SLAVE
   // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
   .SRVAL_Q1(1'b0),
   .SRVAL_Q2(1'b0),
   .SRVAL_Q3(1'b0),
   .SRVAL_Q4(1'b0)
)
ISERDESE2_inst (
   .O(O),                       // 1-bit output: Combinatorial output
   // Q1 - Q8: 1-bit (each) output: Registered data outputs
   .Q1(Q1),
   .Q2(Q2),
   .Q3(Q3),
   .Q4(Q4),
   .Q5(Q5),
   .Q6(Q6),
   .Q7(Q7),
   .Q8(Q8),
   // SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
   .SHIFTOUT1(SHIFTOUT1),
   .SHIFTOUT2(SHIFTOUT2),
   .BITSLIP(BITSLIP),           // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
                                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
                                // to Q8 output ports will shift, as in a barrel-shifter operation, one
                                // position every time Bitslip is invoked (DDR operation is different from
                                // SDR).

   // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
   .CE1(CE1),
   .CE2(CE2),
   .CLKDIVP(CLKDIVP),           // 1-bit input: TBD
   // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
   .CLK(CLK),                   // 1-bit input: High-speed clock
   .CLKB(CLKB),                 // 1-bit input: High-speed secondary clock
   .CLKDIV(CLKDIV),             // 1-bit input: Divided clock
   .OCLK(OCLK),                 // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
   // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
   .DYNCLKDIVSEL(DYNCLKDIVSEL), // 1-bit input: Dynamic CLKDIV inversion
   .DYNCLKSEL(DYNCLKSEL),       // 1-bit input: Dynamic CLK/CLKB inversion
   // Input Data: 1-bit (each) input: ISERDESE2 data input ports
   .D(D),                       // 1-bit input: Data input
   .DDLY(DDLY),                 // 1-bit input: Serial data from IDELAYE2
   .OFB(OFB),                   // 1-bit input: Data feedback from OSERDESE2
   .OCLKB(OCLKB),               // 1-bit input: High speed negative edge output clock
   .RST(RST),                   // 1-bit input: Active high asynchronous reset
   // SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
   .SHIFTIN1(SHIFTIN1),
   .SHIFTIN2(SHIFTIN2)
);

// End of ISERDESE2_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)