Primitive: 1-Bit Look-Up Table with General Output
This design element is a 1-bit look-up table (LUT) with general output (O).
An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attached to the LUT to specify its function. This element provides a look-up table version of a buffer or inverter. These elements are the basic building blocks. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timing models for more accurate pre-layout timing estimation.
The INIT parameter for the FPGA LUT primitive gives the LUT its logical value. By default, this value is zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most cases a new INIT value must be determined in order to specify the logic function for the LUT primitive. There are at least two methods by which the LUT value can be determined.
- The Logic Table Method Create a binary logic table of all possible inputs, specify the desired logic value of the output and then create the INIT string from those output values.
- The Equation Method Define parameters for each input to the LUT that correspond to their listed truth value and use those to build the logic equation you are after. This method is easier to understand once you have grasped the concept and is more self-documenting than the above method. However, this method does require the code to first specify the appropriate parameters.
|INIT = Binary number assigned to the INIT attribute|
Design Entry Method
|INIT||HEX||Any 2-Bit Value||All zeros||Initializes look-up tables.|
VHDL Instantiation Template
Library UNISIM; use UNISIM.vcomponents.all;
-- LUT1: 1-input Look-Up Table with general output -- 7 Series -- Xilinx HDL Language Template, version 2023.1 LUT1_inst : LUT1 generic map ( INIT => "00") port map ( O => O, -- LUT general output I0 => I0 -- LUT input ); -- End of LUT1_inst instantiation
Verilog Instantiation Template
// LUT1: 1-input Look-Up Table with general output (Mapped to a LUT6) // 7 Series // Xilinx HDL Language Template, version 2023.1 LUT1 #( .INIT(2'b00) // Specify LUT Contents ) LUT1_inst ( .O(O), // LUT general output .I0(I0) // LUT input ); // End of LUT1_inst instantiation
- 7 Series FPGAs Configurable Logic Block User Guide (UG474)