LUT5 - 2023.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-05-17
Version
2023.1 English

Primitive: 5-Input look-up Table with General Output

Introduction

This design element is a 5-input, 1-output look-up table (LUT) that can either act as an asynchronous 32-bit ROM (with 5-bit addressing) or implement any 5-input logic function. LUTs are the basic logic building blocks and are used to implement most logic functions of the design. One LUT5 is packed into a LUT6 within a slice, or two LUT5s can be packed into a single LUT6 with some restrictions. The functionality of the LUT5, LUT5_L and LUT5_D is the same. However, the LUT5_L and LUT5_D allow the additional specification to connect the LUT5 output signal to an internal slice or CLB connection using the LO output. The LUT5_L specifies that the only connections from the LUT5 will be within a slice or CLB, while the LUT5_D allows the specification to connect the output of the LUT to both inter-slice/CLB logic and external logic as well. The LUT5 does not state any specific output connections and should be used in all cases except where internal slice or CLB signal connections must be implicitly specified.

An INIT attribute consisting of a 32-bit hexadecimal value must be specified to indicate the LUTs logical function. The INIT value is calculated by assigning a 1 to the corresponding INIT bit value when the associated inputs are applied. For instance, a Verilog INIT value of 32'h80000000 (X"80000000" for VHDL) makes the output zero unless all of the inputs are one (a 5-input AND gate). A Verilog INIT value of 32'hfffffffe (X"FFFFFFFE" for VHDL) makes the output one unless all zeros are on the inputs (a 5-input OR gate).

The INIT parameter for the FPGA LUT primitive gives the LUT its logical value. By default, this value is zero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in most cases a new INIT value must be determined in order to specify the logic function for the LUT primitive. There are at least two methods by which the LUT value can be determined.

  • The Logic Table Method Create a binary logic table of all possible inputs, specify the desired logic value of the output and then create the INIT string from those output values.
  • The Equation Method Define parameters for each input to the LUT that correspond to their listed truth value and use those to build the logic equation you are after. This method is easier to understand once you have grasped the concept and is more self-documenting than the above method. However, this method does require the code to first specify the appropriate parameters.

Logic Table

Inputs Outputs
I4 I3 I2 I1 I0 LO
0 0 0 0 0 INIT[0]
0 0 0 0 1 INIT[1]
0 0 0 1 0 INIT[2]
0 0 0 1 1 INIT[3]
0 0 1 0 0 INIT[4]
0 0 1 0 1 INIT[5]
0 0 1 1 0 INIT[6]
0 0 1 1 1 INIT[7]
0 1 0 0 0 INIT[8]
0 1 0 0 1 INIT[9]
0 1 0 1 0 INIT[10]
0 1 0 1 1 INIT[11]
0 1 1 0 0 INIT[12]
0 1 1 0 1 INIT[13]
0 1 1 1 0 INIT[14]
0 1 1 1 1 INIT[15]
1 0 0 0 0 INIT[16]
1 0 0 0 1 INIT[17]
1 0 0 1 0 INIT[18]
1 0 0 1 1 INIT[19]
1 0 1 0 0 INIT[20]
1 0 1 0 1 INIT[21]
1 0 1 1 0 INIT[22]
1 0 1 1 1 INIT[23]
1 1 0 0 0 INIT[24]
1 1 0 0 1 INIT[25]
1 1 0 1 0 INIT[26]
1 1 0 1 1 INIT[27]
1 1 1 0 0 INIT[28]
1 1 1 0 1 INIT[29]
1 1 1 1 0 INIT[30]
1 1 1 1 1 INIT[31]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute

Port Descriptions

Port Direction Width Function
O Output 1 5-LUT output
I0, I1, I2, I3, I4 Input 1 LUT inputs

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX Any 32-Bit Value All zeros Initializes look-up tables.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- LUT5: 5-input Look-Up Table with general output (Mapped to SliceM LUT6)
--       7 Series
-- Xilinx HDL Language Template, version 2023.1

LUT5_inst : LUT5
generic map (
   INIT => X"00000000") -- Specify LUT Contents
port map (
   O => O,  -- LUT general output
   I0 => I0,   -- LUT input
   I1 => I1,   -- LUT input
   I2 => I2,   -- LUT input
   I3 => I3,   -- LUT input
   I4 => I4    -- LUT input
);

-- End of LUT5_inst instantiation

Verilog Instantiation Template


// LUT5: 5-input Look-Up Table with general output (Mapped to a LUT6)
//       7 Series
// Xilinx HDL Language Template, version 2023.1

LUT5 #(
   .INIT(32'h00000000)  // Specify LUT Contents
) LUT5_inst (
   .O(O),   // LUT general output
   .I0(I0), // LUT input
   .I1(I1), // LUT input
   .I2(I2), // LUT input
   .I3(I3), // LUT input
   .I4(I4)  // LUT input
);

// End of LUT5_inst instantiation

Related Information

  • 7 Series FPGAs Configurable Logic Block User Guide (UG474)