MUXF8 - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: 2-to-1 Look-Up Table Multiplexer with General Output

Introduction

This design element is a two input multiplexer which, in combination with two MUXF7 multiplexers and their four associated LUT6 elements, will let you create any 8-input function, a 16-to-1 multiplexer, or other logic functions up to 24-bits wide. Local outputs of MUXF7 are connected to the I0 and I1 inputs of the MUXF8. The S input is driven from any internal net. When Low, S selects I0. When High, S selects I1.

The O output is a general interconnect.

Logic Table

Inputs Outputs
S I0 I1 O
0 I0 X I0
1 X I1 I1
X 0 0 0
X 1 1 1

Port Descriptions

Port Direction Width Function
O Output 1 Output of MUX to general routing.
I0 Input 1 Input (tie to MUXF7 LO out).
I1 Input 1 Input (tie to MUXF7 LO out).
S Input 1 Input select to MUX.

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- MUXF8: CLB MUX to tie two MUXF7's together with general output
--        7 Series
-- Xilinx HDL Language Template, version 2023.2

MUXF8_inst : MUXF8
port map (
   O => O,    -- Output of MUX to general routing
   I0 => I0,  -- Input (tie to MUXF7 L/LO out)
   I1 => I1,  -- Input (tie to MUXF7 L/LO out)
   S => S     -- Input select to MUX
);

-- End of MUXF8_inst instantiation

Verilog Instantiation Template


// MUXF8: CLB MUX to tie two MUXF7's together with general output
//        7 Series
// Xilinx HDL Language Template, version 2023.2

MUXF8 MUXF8_inst (
   .O(O),    // Output of MUX to general routing
   .I0(I0),  // Input (tie to MUXF7 L/LO out)
   .I1(I1),  // Input (tie to MUXF7 L/LO out)
   .S(S)     // Input select to MUX
);

// End of MUXF8_inst instantiation

Related Information

  • 7 Series FPGAs Configurable Logic Block User Guide (UG474)