OBUFDS - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: Differential Signaling Output Buffer

Introduction

This design element is a single output buffer that supports low-voltage, differential signaling. OBUFDS isolates the internal circuit and provides drive current for signals leaving the chip. Its output is represented as two distinct ports (O and OB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET and MYNETB).

Logic Table

Inputs Outputs
I O OB
0 0 1
1 1 0

Port Descriptions

Port Direction Width Function
O Output 1 Diff_p output (connect directly to top level port).
OB Output 1 Diff_n output (connect directly to top level port).
I Input 1 Buffer input.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
SLEW STRING "SLOW" or "FAST" "SLOW" Specifies the slew rate of the output driver. Consult the product Data Sheet for recommendations of the best setting for this attribute.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- OBUFDS: Differential Output Buffer
--         7 Series
-- Xilinx HDL Language Template, version 2023.2

OBUFDS_inst : OBUFDS
generic map (
   IOSTANDARD => "DEFAULT", -- Specify the output I/O standard
   SLEW => "SLOW")          -- Specify the output slew rate
port map (
   O => O,     -- Diff_p output (connect directly to top-level port)
   OB => OB,   -- Diff_n output (connect directly to top-level port)
   I => I      -- Buffer input
);

-- End of OBUFDS_inst instantiation

Verilog Instantiation Template


// OBUFDS: Differential Output Buffer
//         7 Series
// Xilinx HDL Language Template, version 2023.2

OBUFDS #(
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW")           // Specify the output slew rate
) OBUFDS_inst (
   .O(O),     // Diff_p output (connect directly to top-level port)
   .OB(OB),   // Diff_n output (connect directly to top-level port)
   .I(I)      // Buffer input
);

// End of OBUFDS_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)