OBUFT - 2023.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-05-17
Version
2023.1 English

Primitive: 3-State Output Buffer with Active Low Output Enable

Introduction

This design element is a single, 3-state output buffer with input I, output O, and active-Low output enables (T). This element uses the LVCMOS18 standard and has selectable drive and slew rates using the DRIVE and SLOW or FAST constraints.

When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, the output is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is needed with a 3-state capability, such as the case when building bidirectional I/O.

Logic Table

Inputs Outputs
T I O
1 X Z
0 1 1
0 0 0

Port Descriptions

Port Direction Width Function
O Output 1 Buffer output (connect directly to top-level port).
I Input 1 Buffer input.
T Input 1 3-state enable input.

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DRIVE INTEGER 2, 4, 6, 8, 12, 16, 24 12 Specifies the output current drive strength of the I/O. It is suggested that you set this to the lowest setting tolerable for the design drive and timing requirements.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
SLEW STRING "SLOW" or "FAST" "SLOW" Specifies the slew rate of the output driver. See the Data Sheet for recommendations of the best setting for this attribute.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- OBUFT: Single-ended 3-state Output Buffer
--        7 Series
-- Xilinx HDL Language Template, version 2023.1

OBUFT_inst : OBUFT
generic map (
   DRIVE => 12,
   IOSTANDARD => "DEFAULT",
   SLEW => "SLOW")
port map (
   O => O,     -- Buffer output (connect directly to top-level port)
   I => I,     -- Buffer input
   T => T      -- 3-state enable input
);

-- End of OBUFT_inst instantiation

Verilog Instantiation Template


// OBUFT: Single-ended 3-state Output Buffer
//        All devices
// Xilinx HDL Language Template, version 2023.1

OBUFT #(
   .DRIVE(12),   // Specify the output drive strength
   .IOSTANDARD("DEFAULT"), // Specify the output I/O standard
   .SLEW("SLOW") // Specify the output slew rate
) OBUFT_inst (
   .O(O),     // Buffer output (connect directly to top-level port)
   .I(I),     // Buffer input
   .T(T)      // 3-state enable input
);

  // End of OBUFT_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)