ODDR - 2022.1 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
Release Date
2022.1 English

Primitive: Dedicated Dual Data Rate (DDR) Output Register


This design element is a dedicated output register for use in transmitting double data rate (DDR) signals from FPGA devices. The ODDR interface with the FPGA fabric is not limited to opposite clock edges. It can be configured to present date from the FPGA fabric at the same clock edge. This feature allows designers to avoid additional timing complexities and CLB usage. The ODDR also works with SelectIO™ features.

ODDR Modes

This element has two modes of operation. These modes are set by the DDR_CLK_EDGE attribute.

  • OPPOSITE_EDGE mode The data transmit interface uses classic DDR methodology. Given a data and clock at pin D1-2 and C respectively, D1 is sampled at every positive edge of clock C and D2 is sampled at every negative edge of clock C. Q changes every clock edge.

  • SAME_EDGE mode Data is still transmitted at the output of the ODDR by opposite edges of clock C. However, the two inputs to the ODDR are clocked with a positive clock edge of clock signal C and an extra register is clocked with a negative clock edge of clock signal C. Using this feature, DDR data can now be presented into the ODDR at the same clock edge.

Port Descriptions

Port Direction Width Function
Q Output 1 Data Output (DDR): The ODDR output that connects to the IOB pad.
C Input 1 Clock Input: The C pin represents the clock input pin.
CE Input 1 Clock Enable Input: When asserted High, this port enables the clock input on port C.
D1 : D2 Input 1 (each) Data Input: This pin is where the DDR data is presented into the ODDR module.
R Input 1 Reset: Depends on how SRTYPE is set.
S Input 1 Set: Active-High asynchronous set pin. This pin can also be Synchronous depending on the SRTYPE attribute.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
DDR_CLK_EDGE STRING "OPPOSITE_EDGE", "SAME_EDGE" "OPPOSITE_EDGE" DDR clock mode recovery mode selection.
INIT INTEGER 0, 1 0 Q initialization value.
SRTYPE STRING "SYNC", "ASYNC" "SYNC" Set/Reset type selection.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- ODDR: Output Double Data Rate Output Register with Set, Reset
--       and Clock Enable.
--       7 Series
-- Xilinx HDL Language Template, version 2022.1

ODDR_inst : ODDR
generic map(
   INIT => '0',   -- Initial value for Q port ('1' or '0')
   SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map (
   Q => Q,   -- 1-bit DDR output
   C => C,    -- 1-bit clock input
   CE => CE,  -- 1-bit clock enable input
   D1 => D1,  -- 1-bit data input (positive edge)
   D2 => D2,  -- 1-bit data input (negative edge)
   R => R,    -- 1-bit reset input
   S => S     -- 1-bit set input

-- End of ODDR_inst instantiation

Verilog Instantiation Template

// ODDR: Output Double Data Rate Output Register with Set, Reset
//       and Clock Enable.
//       7 Series
// Xilinx HDL Language Template, version 2022.1

   .INIT(1'b0),    // Initial value of Q: 1'b0 or 1'b1
   .SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
   .Q(Q),   // 1-bit DDR output
   .C(C),   // 1-bit clock input
   .CE(CE), // 1-bit clock enable input
   .D1(D1), // 1-bit data input (positive edge)
   .D2(D2), // 1-bit data input (negative edge)
   .R(R),   // 1-bit reset
   .S(S)    // 1-bit set

// End of ODDR_inst instantiation

Related Information

  • See the 7 Series FPGA SelectIO Resources User Guide (UG471).