SRLC32E - 2022.1 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
Release Date
2022.1 English

Primitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) with Clock Enable


This design element is a shift register look-up table (LUT). The inputs A4, A3, A2, A1, and A0 select the depth of the shift register.

The shift register can be of a fixed, static depth or it can be dynamically adjusted.

To create a fixed-depth shift register: Drive the A4 through A0 inputs with static values. The depth of the shift register can vary from 1 bit to 32 bits, as determined by the following formula:

Depth = (16 x A4) + (8 x A3) + (4 x A2) + (2 x A1) + A0 + 1

If A4, A3, A2, A1, and A0 are all zeros (00000), the shift register is one bit deep. If they are all ones (11111), it is 32 bits deep.

To change the depth of the shift register dynamically: Change the values driving the A4 through A0 inputs. For example, if A3, A2, A1, and A0 are all ones (1111) and A4 toggles between a one (1) and a zero (0), the depth of the shift register changes from 32 bits to 16 bits. Internally, the depth of the shift register is always 32 bits and the input lines A4 through A0 select which of the 32 bits reach the output. The shift register LUT contents are initialized by assigning a eight-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of eight zeros (00000000) so that the shift register LUT is cleared during configuration.

When CE is High, the data (D) is loaded into the first bit of the shift register during the clock (CLK) transition. During subsequent clock transitions, when CE is High, data shifts to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. When CE is Low, the register ignores clock transitions and retains current data within the shift register.

Two or more SLRC32E components may be cascaded to create deeper than 32-bit shift registers. To do so, connect the Q31 output of one SRLC32E component to the D input of another.

Note: When using SRLs with initialized values, you should use safe clock start-up techniques to ensure the initialized data is not corrupted upon completion of configuration. Refer to UG949: UltraFast Design Methodology Guide for details on controlling and synchronizing clock startup.

Port Descriptions

Port Direction Width Function
A<4:0> Input 5 The value placed on the A0 - A3 inputs specifies the shift register depth.

Depth = (16 x A4) + (8 x A3) + (4 x A2) + (2 x A1) + A0 + 1

CE Input 1 Active-High clock enable.
CLK Input 1 Shift register clock. Polarity is determined by the IS_CLK_INVERTED attribute.
D Input 1 SRL data input.
Q Output 1 SRL data output.
Q31 Output 1 SRL data output used to connect more than one SRLC32E component to form deeper than 32-bit shift registers.

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX Any 32-Bit Value All zeros Specifies the initial contents in the shift register upon completion of configuration.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- SRLC32E: 32-bit variable length shift register LUT
--          with clock enable (Mapped to a SliceM LUT6)
--          7 Series
-- Xilinx HDL Language Template, version 2022.1

SRLC32E_inst : SRLC32E
generic map (
   INIT => X"00000000")
port map (
   Q => Q,        -- SRL data output
   Q31 => Q31,    -- SRL cascade output pin
   A => A,        -- 5-bit shift depth select input
   CE => CE,      -- Clock enable input
   CLK => CLK,    -- Clock input
   D => D         -- SRL data input

-- End of SRLC32E_inst instantiation

Verilog Instantiation Template

// SRLC32E: 32-bit variable length cascadable shift register LUT  (Mapped to a SliceM LUT6)
//          with clock enable
//          7 Series
// Xilinx HDL Language Template, version 2022.1

SRLC32E #(
   .INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
   .Q(Q),     // SRL data output
   .Q31(Q31), // SRL cascade output pin
   .A(A),     // 5-bit shift depth select input
   .CE(CE),   // Clock enable input
   .CLK(CLK), // Clock input
   .D(D)      // SRL data input

// End of SRLC32E_inst instantiation

Related Information

  • See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).