The Xilinx n-tap 2 Channel Decimate by 2 MAC FIR Filter reference block implements a multiply-accumulate-based FIR filter. One dedicated multiplier and one Dual Port Block RAM are used in the n-tap filter. The same MAC engine is used to process both channels that are time division multiplexed (TDM) together. Completely different coefficient sets can be specified for each channel as long as they have the same number of coefficients. The filter also provides a fixed decimation by 2 using a polyphase filter technique. The filter configuration helps illustrate techniques for storing multiple coefficient sets and data samples in filter design. The Virtex FPGA family (and Virtex family derivatives) provide dedicated circuitry for building fast, compact adders, multipliers, and flexible memory architectures. The filter design takes advantage of these silicon features by implementing a design that is compact and resource efficient.
Implementation details are provided in the filter design Subsystems. To read the annotations, place the block in a model, then right-click on the block and select Explore from the popup menu. Double click on one of the sub-blocks to open the sub-block model and read the annotations.
The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.
Parameters specific to this reference block are as follows:
- Data Input Bit Width: Width of input sample.
- Data Input Binary Point: Binary point location of input.
- Coefficient Vector (Ch.1): Specify coefficients for Channel 1 of the filter. Number of taps is inferred from size of coefficient vector.
- Coefficient Vector (Ch.2): Specify coefficients for Channel 2 of the filter. Number of taps is inferred from size of coefficient vector.
- Number of Bits per Coefficient: Bit width of each coefficient.
- Binary Point per Coefficient: Binary point location for each coefficient.
- Sample Period: Sample period of input
J. Hwang and J. Ballagh. Building Custom FIR Filters Using System Generator. 12th International Field-Programmable Logic and Applications Conference (FPL). Montpellier, France, September 2002. Lecture Notes in Computer Science 2438