The Xilinx 4n-tap MAC FIR Filter reference block implements a multiply-accumulate-based FIR filter. The three filter configurations help illustrate the tradeoffs between filter throughput and device resource consumption. The Virtex FPGA family (and Virtex family derivatives) provide dedicated circuitry for building fast, compact adders, multipliers, and flexible memory architectures. Each filter design takes advantage of these silicon features by implementing a design that is compact and resource efficient.
Implementation details are provided in the filter design Subsystems. To read the annotations, place the block in a model, then right-click on the block and select Explore from the popup menu. Double click on one of the sub-blocks to open the sub-block model and read the annotations.
The block parameters dialog box can be invoked by double-clicking the icon in your Simulink model.
Parameters specific to this reference block are as follows:
- Coefficients: Specify coefficients for the filter. Number of taps is inferred from size of coefficient vector.
- Number of Bits per Coefficient: Bit width of each coefficient.
- Binary Point for Coefficient: Binary point location for each coefficient.
- Number of Bits per Input Sample: Width of input sample.
- Binary Point for Input Samples: Binary point location of input.
- Input Sample Period: Sample period of input.
J. Hwang and J. Ballagh. Building Custom FIR Filters Using System Generator. 12th International Field-Programmable Logic and Applications Conference (FPL). Montpellier, France, September 2002. Lecture Notes in Computer Science 2438.