SRL16E - 2022.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
UG974
Release Date
2022-04-20
Version
2022.1 English

Primitive: 16-Bit Shift Register Look-Up Table (LUT)

• PRIMITIVE_GROUP: CLB
• PRIMITIVE_SUBGROUP: SRL
• Families: UltraScale, UltraScale+

Introduction

This design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the depth of the shift register.

The shift register can be of a fixed, static depth or it can be dynamically adjusted.

To create a fixed-depth shift register: Drive the A3 through A0 inputs with static values. The depth of the shift register can vary from 1 bit to 16 bits, as determined by the following formula:

Depth = (8 * A3) + (4 * A2) + (2 * A1) + A0 + 1

If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit deep. If they are all ones (1111), it is 16 bits deep.

To change the depth of the shift register dynamically: Change the values driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), the depth of the shift register changes from 16 bits to 8 bits. Internally, the depth of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output. The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

When CE is High, the data (D) is loaded into the first bit of the shift register during the clock (CLK) transition. During subsequent clock transitions, when CE is High, data shifts to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached. When CE is Low, the register ignores clock transitions and retains current data within the shift register.

Two SLR16E components can be placed within the same LUT within a CLBM as long as they have the same clock, clock enable and depth selection address signals as well as the same IS_CLK_INVERTED attribute value. This allows up to 16 SRL16E components to be placed into a single CLB. Optionally, LUTNM or HLUTNMs can be placed on two SRL16E components to specify specific grouping within a LUT.
Note: When using SRLs with initialized values, you should use safe clock start-up techniques to ensure the initialized data is not corrupted upon completion of configuration. Refer to the UltraFast Design Methodology Guide for the Vivado Design Suite (UG949)for details on controlling and synchronizing clock startup.

Inputs Output
Am CE CLK D Q
Am 0 X X Q(Am)
Am 1 D Q(Am - 1)

m= 0, 1, 2, 3

Port Descriptions

Port Direction Width Function
CE Input 1 Active-High clock enable
CLK Input 1 Shift register clock. Polarity is determined by the IS_CLK_INVERTED attribute.
D Input 1 SRL data input.
Q Output 1 SRL data output.
Depth Selection: The value placed on the A0 - A3 inputs specifies the shift register depth. Depth = (8 * A3) + (4 * A2) + (2 * A1) + A0 + 1
A0 Input 1 The value placed on the A0 - A3 inputs specifies the shift register depth. Depth = (8 * A3) + (4 * A2) + (2 * A1) + A0 + 1
A1 Input 1 The value placed on the A0 - A3 inputs specifies the shift register depth. Depth = (8 * A3) + (4 * A2) + (2 * A1) + A0 + 1
A2 Input 1 The value placed on the A0 - A3 inputs specifies the shift register depth. Depth = (8 * A3) + (4 * A2) + (2 * A1) + A0 + 1
A3 Input 1 The value placed on the A0 - A3 inputs specifies the shift register depth. Depth = (8 * A3) + (4 * A2) + (2 * A1) + A0 + 1

Design Entry Method

 Instantiation Yes Inference Recommended IP and IP Integrator Catalog No

Available Attributes

Attribute Type Allowed Values Default Description
INIT HEX 16'h0000 to 16'hffff 16'h0000 Specifies the initial contents in the shift register upon completion of configuration.
IS_CLK_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the clock pin (CLK) of this component. When set to 1 the active edge of the clock is the falling edge. If an external inverter is connected to this pin, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the clock polarity.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
``````Library UNISIM;
use UNISIM.vcomponents.all;``````
``````
-- SRL16E: 16-Bit Shift Register Look-Up Table (LUT)
--         UltraScale
-- Xilinx HDL Language Template, version 2022.1

SRL16E_inst : SRL16E
generic map (
INIT => X"0000",        -- Initial contents of shift register
IS_CLK_INVERTED => '0'  -- Optional inversion for CLK
)
port map (
Q => Q,     -- 1-bit output: SRL Data
CE => CE,   -- 1-bit input: Clock enable
CLK => CLK, -- 1-bit input: Clock
D => D,     -- 1-bit input: SRL Data
-- Depth Selection inputs: A0-A3 select SRL depth
A0 => A0,
A1 => A1,
A2 => A2,
A3 => A3
);

-- End of SRL16E_inst instantiation
``````

``````
// SRL16E: 16-Bit Shift Register Look-Up Table (LUT)
//         UltraScale
// Xilinx HDL Language Template, version 2022.1

SRL16E #(
.INIT(16'h0000),        // Initial contents of shift register
.IS_CLK_INVERTED(1'b0)  // Optional inversion for CLK
)
SRL16E_inst (
.Q(Q),     // 1-bit output: SRL Data
.CE(CE),   // 1-bit input: Clock enable
.CLK(CLK), // 1-bit input: Clock
.D(D),     // 1-bit input: SRL Data
// Depth Selection inputs: A0-A3 select SRL depth
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3)
);

// End of SRL16E_inst instantiation
``````

Related Information

• See the UltraScale Architecture Configurable Logic Block User Guide (UG574).
• See the UltraFast Design Methodology Guide for the Vivado Design Suite (UG949).