Xilinx Parameterized Macros - 2022.1 English

UltraScale Architecture Libraries Guide (UG974)

Document ID
Release Date
2022.1 English

About Xilinx Parameterized Macros

This section describes Xilinx Parameterized Macros that can be used with UltraScaleā„¢ architecture-based devices. The macros are organized alphabetically.
Important: Unimacros from previous generation Xilinx FPGA architectures are not supported in the Ultrascale architecture and have been replaced by Xilinx Parameterized Macros.

The following information is provided for each macro, where applicable:

  • Name, description, macro group, macro subgroup, and family
  • Schematic symbol
  • Introduction
  • Logic diagram (if any)
  • Port descriptions
  • Design Entry Method
  • Available attributes
  • Example instantiation templates
  • Links to additional information

Enabling Xilinx Parameterized Macros

The following instructions describe how to prepare Vivado to use the XPM libraries.
  1. Ensure Vivado can identify the XPMs.
    • When using the IDE and/or the project flow, the tools will parse the files added to the project and setup Vivado to recognize the XPMs.
    • When using the non-project flow, you must issue the auto_detect_xpm command.
  2. Select the XPM template that you wish to use from below.
  3. Copy the contents of the template and paste into your own source file.
  4. Set parameters/generics, and wire ports according to the documentation provided as code comments.
Note: Be sure to read and comply with all code comments to properly use the XPMs.


A testbench for XPM CDC macros is available in the XPM CDC Testbench File .

A testbench for XPM FIFO macros is available in the XPM FIFO Testbench File .

Instantiation Templates

Instantiation templates for Xilinx Parameterized Macros are also available in Vivado, as well as in a downloadable ZIP file. Because PDF includes headers and footers if you copy text that spans pages, you should copy templates from Vivado or the downloaded ZIP file whenever possible.

Instantiation templates can be found on the Web in the Instantiation Templates for Xilinx Parameterizable Macros file.

List of Xilinx Parameterized Macros

XPM_CDC_ARRAY_SINGLE Parameterized Macro: Single-bit Array Synchronizer CDC
XPM_CDC_ASYNC_RST Parameterized Macro: Asynchronous Reset Synchronizer CDC
XPM_CDC_GRAY Parameterized Macro: Synchronizer via Gray Encoding CDC
XPM_CDC_HANDSHAKE Parameterized Macro: Bus Synchronizer with Full Handshake CDC
XPM_CDC_PULSE Parameterized Macro: Pulse Transfer CDC
XPM_CDC_SINGLE Parameterized Macro: Single-bit Synchronizer CDC
XPM_CDC_SYNC_RST Parameterized Macro: Synchronous Reset Synchronizer CDC
XPM_FIFO_ASYNC Parameterized Macro: Asynchronous FIFO FIFO
XPM_FIFO_AXIF Parameterized Macro: AXI-Full FIFO FIFO
XPM_FIFO_AXIL Parameterized Macro: AXI-Lite FIFO FIFO
XPM_FIFO_AXIS Parameterized Macro: AXI Stream FIFO FIFO
XPM_FIFO_SYNC Parameterized Macro: Synchronous FIFO FIFO
XPM_MEMORY_DPDISTRAM Parameterized Macro: Dual Port Distributed RAM Memory
XPM_MEMORY_DPROM Parameterized Macro: Dual Port ROM Memory
XPM_MEMORY_SDPRAM Parameterized Macro: Simple Dual Port RAM Memory
XPM_MEMORY_SPRAM Parameterized Macro: Single Port RAM Memory
XPM_MEMORY_SPROM Parameterized Macro: Single Port ROM Memory
XPM_MEMORY_TDPRAM Parameterized Macro: True Dual Port RAM Memory