Creating Ports - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English
  1. To use the Create Port option, right-click and select Create Port, as shown in the following figure.

    This feature is used for connecting individual signals, such as a clock, reset, and uart_txd. The Create Port option gives you more control in specifying the input and output, the bit-width and the type (for example clk, reset, interrupt, data, and clock enable).



    The Create Port dialog box opens, as shown in the following figure.



  2. Specify the Port name, the Direction, such as Input, Output or Bidirectional, and the Type (for example Clock, Reset, Interrupt, Data, ClockEnable, or Custom type). For clock ports you must specify a Frequency value in MHz. If you are using the Tcl flow to create the clock port, you must use the -freq_hz argument to specify a frequency value. If you do not provide a -freq_hz value, the following warning message appears.
    WARNING: [BD 5-670] It is required to provide a frequency value for a user created input clock port. Please use the <-freq_hz $freq_val> argument of the create_bd_port command. ie create_bd_port -dir I -type clk -freq_hz 100000000 clkin
    /my_clock1

    You can also create a bit-vector by checking the Create vector field and then selecting the appropriate bit-width. You can also specify the Interrupt type and Sensitivity for interrupt pins. Likewise, you can specify the Polarity of the reset ports. Finally, use the Connect to <pin_name> selected pin check box to connect to an existing pin of a cell in the block design.