Creating a Design with GT IP - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

For Versal Adaptive SoC, GT components are updated from Common/Channel to a GT Quad granularity. To enable some of the GT sharing use cases, GT wizard flows use the Vivado IP integrator. You can use the Vivado IP integrator to build system designs using single or multiple GT Quads.

The Versal Adaptive SoC Transceivers Wizard IP solution helps configure one or more serial transceivers. The Transceivers Wizard solution contains the following cores:

Transceivers Bridge
A reference parent IP (Bridge IP) that configures Transceivers Wizard.
Transceivers Wizard
A wrapper around the GT*_QUAD primitive. It consists of single GT Quad (GT quad base IP). Multiple Transceivers Wizards are instantiated for multi-lane (greater than 4 lanes) designs.
Note: The GT Wizard does not add physical locations for GT Quads. Instead, the I/O Planner is used to add GT I/O and GT reference clock pin locations.

For more information on GTs, see the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331), Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002), and Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017). For guidance on GT selection and pin planning for CPM5, see Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).

The GT Wizard does not add physical locations for GT Quads. Instead, the Hard Block Planner is used to add physical GT locations and GT reference clock pin locations. For information on the Hard Block Planner, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899). For information on the full GT quad layout and supported configuration options, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).