- Create a new Vivado project, and select
Post-synthesis Project in the New Project Wizard, as
shown in the following figure.
Note: If the Do not specify sources at this time option is enabled, you can add design sources after project creation.
- Click Next.
The Add Sources dialog box opens, as shown in the following figure.
- In the Add Netlist Sources Page click the ‘+’ sign to Add Files,
as seen in the following figure.
- Select the EDIF netlist for the top-level design, and click OK.
- Using Add Files button or the + sign add the block design file
(for which a DCP was created earlier) as well.
As the block design is added, all the relevant constraints and the DCP file for the block design are picked up by Vivado. The block design is not be re-synthesized. The constraints, however, are reprocessed.
- Click Next.
- On the Add Constraints page, add any constraints files (XDC) that are needed for the project, and click Next.
- Specify the target part or target platform board as required by
the project, and click Next. Important: The target part or platform board for the post-synthesis project must be the same as the project in which the block design was created. If the target parts are different, even within the same device family, the IP used in the block design will be locked, and the design must be re-generated. In that case the behavior of the new block design might not be the same as the original block design.
- Verify all the information for the project as presented on the
New Project Summary page, and click Finish. Note: When a block design is added to a netlist project, the block design is “locked.” Accordingly, you cannot edit the block design, upgrade it or perform other actions. The block design also needs to be fully generated for it to be a part of a netlist project.
The next step is to create a post-synthesis project in the Vivado IDE. See this link in Vivado Design Suite User Guide: System-Level Design Entry (UG895) for more information.