A Vitis™ platform project begins with a Vivado Design Suite project file (<platform>.xpr) as the starting point to build the Xilinx® Support Archive (XSA) file for hardware components.
After the project is created, a block design must be created. The block design is used to instantiate the necessary IP to create the hardware portion of the platform. As an example, the following figure shows the block design for the base platform, ZC702, provided in the Vivado IP integrator.
There are a few things worth noticing in the block design above:
- The synchronized resets from the Processor System Reset blocks are not used anywhere in the design.
- Likewise, the input to the Concat block that is supposed to connect to interrupt sources are not connected.
These input and output pins are to be used by the hardware functions. If a hardware function uses a particular clock then it uses the synchronized reset output for that clock. After the hardware functions are built by the Vitis tool, a final block design containing the hardware functions (packaged as an HLS IP) is instantiated in this block design, and all the necessary connections to clock, resets, interrupts and any AXI Interconnect needed are connected appropriately by the Vitis build scripts.