When you use the standard naming convention for an AXI interface (recommended), the Vivado IP integrator automatically infers the interface. As an example, the following code sample shows standard AXI names being used.
When this RTL module is added to the block design the AXI interface is automatically inferred as shown below.
After an AXI interface is inferred for a module, the Connection Automation feature of IP integrator becomes available for the module. This feature offers connectivity options to connect a slave interface to a master interface, or the master to the slave.
If the names of your ports do not match with standard AXI interface names, you can force the creation of an interface and map the physical ports to the logical ports by using the X_INTERFACE_INFO attribute as found in the Language Templates.
Expand the appropriate HDL language Verilog/VHDL > IP Integrator HDL and select the appropriate AXI Interface to see the attributes in the Preview pane. As an example, the following figure shows the VHDL language template for the AXI4 interface listing the attributes that need to be inserted into the module definition.
If the same AXI clock is to be associated with a slave as well as a master interface, the clock should be called axi_aclk or axis_aclk instead of calling the clock s_axis_aclk or m_axis_aclk. Keeping the prefix "m_" and "s_" out from the clock name infers that the clock is to be associated with both master and slave AXI interfaces. As an example in the following figure an IP is shown with a AXI streaming slave and an AXI streaming master interface.
If you look at the Block Interface Properties window for the slave interface, s_axis, it shows that the Associated clock is s_axis_aclk.
If you look at the properties of the m_axis interface, the Associated clock value is set to None.
To auto associate the s_axis_aclk to both the s_axis and the m_axis interfaces, rename the clock in your RTL code to axis_aclk. As you can see now the clock is associated to the m_axis interface as well.