Inferring Control Signals in a RTL Module - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

You must insert attributes into the HDL code so that clocks, resets, interrupts, and clock enable are correctly inferred. The AMD Vivado™ Design Suite provides language templates for these attributes. To access these templates, click Language Templates under the Project Manager.

Figure 1. Select Language Templates

This opens up the Language Templates dialog box, as shown in the following figure.

Figure 2. Language Templates Dialog Box

You can expand the appropriate HDL language Verilog/VHDL > IP Integrator HDL > and select the appropriate Signal Interface to see the attributes in the Preview pane. As an example, the VHDL language template for the clock interface shows the following attributes that need to be inserted in the module definition.



ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of <clock_port_name>: SIGNAL is
"xilinx.com:signal:clock:1.0 <clock_port_name> CLK";
-- Supported parameters: ASSOCIATED_CLKEN, ASSOCIATED_RESET,
ASSOCIATED_ASYNC_RESET, ASSOCIATED_BUSIF, CLK_DOMAIN, PHASE, FREQ_HZ
-- Most of these parameters are optional. However, when using AXI, at least
one clock must be associated to the AXI interface.
-- Use the axi interface name for ASSOCIATED_BUSIF, if there are multiple
interfaces, separate each name by ':'
-- Use the port name for ASSOCIATED_RESET.
-- Output clocks will require FREQ_HZ to be set (note the value is in HZ
and an integer is expected).
--  Setting FREQ_TOLERANCE_HZ to 0 would allow FREQ_HZ value i:e 100000000 frequency only on the port, setting to FREQ_HZ value would allow FREQ_HZ within range from  FREQ_HZ-10MHz to FREQ_HZ+10MHz, setting to ‘-1’ would allow any FREQ_HZ value on the clock port from the top BD.
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of <clock_port_name>: SIGNAL is
"ASSOCIATED_BUSIF <AXI_interface_name>, ASSOCIATED_RESET <reset_port_name>,
FREQ_HZ 100000000,FRED_TOLERENCE_HZ 0";

Insert these attributes in the HDL code for the module, as shown in the following figure, which shows the declaration of the attributes and the definition of attribute values for both the clock and reset signals.

Figure 3. Inserting Attributes for Inferring Control Signals

In the code sample shown above, a clock port called clk_in is present in the RTL code. To infer the clk_in port as a clock pin you need to insert the following attributes:


-- Declare attributes for clocks and resets
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_in: SIGNAL is
"xilinx.com:signal:clock:1.0 clk_in
CLK";
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER of clk_in : SIGNAL is "ASSOCIATED_RESET
reset_in,
FREQ_HZ 100000000,
FREQ_TOLERENCE_HZ 0";

The clk_in clock signal is associated with the reset_in reset signal in the attributes shown above. You can click on a pin of a module symbol to see the various associated properties, as shown in the following figure.

Figure 4. Inspect Inferred Properties of a Clock Pin

Attributes to infer reset signals are also inserted in the HDL code. Reset signals with names that end with 'n', such as resetn and aresetn, infer an ACTIVE_LOW signal. The tool automatically defines the POLARITY parameter on the interface to ACTIVE_LOW. This parameter is used in the Vivado IP integrator to determine if the reset is properly connected when the block diagram is generated. For all other reset interfaces, the POLARITY parameter is not defined, and is instead determined by the parameter propagation feature of IP integrator. See Propagating Parameters in IP Integrator, for more information.

Tip: You can use the X_INTERFACE_PARAMETER attribute to force the polarity of the signal to another value.

You can also see what IP integrator has inferred for a referenced module by right-clicking an instance, and selecting Refresh Module from the context menu, or by using the following update_module_reference Tcl command:


update_module_reference design_1_my_dff8_inst_1_0

This reloads the RTL module, and the Tcl Console displays messages indicating what was inferred:


INFO: [IP_Flow 19-5107] Inferred bus interface 'clk_in' of definition 
'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-4728] Bus Interface 'clk_in': Added interface parameter 
'ASSOCIATED_RESET' with value 'reset_in'.
INFO: [IP_Flow 19-4728] Bus Interface 'clk_in': Added interface parameter 'FREQ_HZ' 
with value '100000000'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'reset_in' of definition 
'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-4728] Bus Interface 'reset_in': Added interface parameter 
'POLARITY' with value 'ACTIVE_HIGH'.

This command can also force the RTL module to be updated from the source file. If the source code already contains these attributes prior to instantiating the module in the block design, you see what is being inferred on the Tcl Console.

You might want to disable automatic port inferencing. For such cases, you can use the X_INTERFACE_IGNORE attribute. The syntax for VHDL is as follows:


ATTRIBUTE X_INTERFACE_IGNORE:STRING;
ATTRIBUTE X_INTERFACE_IGNORE OF <port_name>: SIGNAL IS "TRUE";

The syntax for Verilog is as follows:


(* X_INTERFACE_IGNORE = "true" *)
input <port_name>,