Limitations of the Module Reference Feature - 2022.1 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
Release Date
2022.1 English

The following limitations exist in the Module Reference feature:

  • Because a module reference is not an IP, you cannot specify the Vendor, Library, Name, and Version (VLNV).
  • VHDL and Verilog are the only supported languages for module definition. A block design containing a module reference cannot be packaged as an IP. Instead, package the module as an IP separately, and then package the BD including that IP.
  • Module Reference blocks cannot be opted out of upgrade while migrating a design from a previous version of Vivado.
  • A ModuleRef must not contain CIPS or NOC IP.
  • A ModuleRef cannot instantiate one or more DCP modules.
  • A ModuleRef cannot instantiate one or more ModuleRefs (Nested ModuleRefs).
  • A ModuleRef cannot instantiate a BD using block design container (BDC) technology.
Tip: SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the top-level of the RTL module.

Known Issues in 2022.1

  • Associated ELF files do not show in the GUI for BD module references. This is only a GUI issue, the MB processor and ELF files advertised correctly from Tcl.
  • The assigned addresses to/from an RTL module reference are lost when "Refresh Module References" is clicked. Assign the address manually.
  • Hardware handoff issues when BD with MicroBlaze processor are packaged as IP or added as RTL module ref in another.