Parameter Mismatch Example - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English

The following is an example of a parameter mismatch on the FREQ_HZ property of a clock pin. In this example, the frequency does not match between the S01_AXI port and the S_AXI interface of the AXI Interconnect. This error is revealed when the design is validated.

Figure 1. FREQ_HZ Property Mismatch Between Port and Interface Pin

  • The S01_AXI port has a frequency of 200 MHz as can be seen in the properties window.
  • The S01_AXI interface of the AXI Interconnect is set to a frequency of 100 MHz.

You can fix this error by changing the frequency in the property, or by double-clicking the S01_AXI port and correcting the frequency in the Frequency field of the customization dialog box.

Figure 2. Change Frequency Port in Properties Window

After you change the frequency, re-validate the design to ensure there are no errors.