Removing Debug Logic after Debug - 2023.2 English

Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

Document ID
UG994
Release Date
2023-10-18
Version
2023.2 English
You can remove debug logic in several different ways, depending on the chosen flow:
  • If HDL instantiation was done with System ILA, then select and right-click the net marked for debug in the block design.
  • Clear Debug option can be selected from the context menu. This removes the connection between the net marked for debug and the System ILA and also re-configures the ILA to debug only the other nets. If there are no nets to be debugged, then the System ILA is deleted.

In some cases, you might want to keep the debugging logic within the block design as it is, but, want to exclude the debugging logic from the generated HDL. To support this, block designs have an EXCLUDE_DEBUG_LOGIC property, which can be enabled in the Properties window or through the set_property Tcl command, specified as follows:

set_property EXCLUDE_DEBUG_LOGIC 1 [get_files 
C:/Temp/base_mb_kc705/base_mb_kc705.srcs/sources_1/bd/base_mb/base_mb.bd]

With the block design selected in the Sources window, check the EXCLUDE_DEBUG_LOGIC property in the Source File Properties window, as shown in the following figure.

Figure 1. Excluding Debug Logic from Generation

If netlist insertion flow was used to insert an ILA after synthesis, then you must remove the ILA manually. To do this, open the netlist after synthesis and in the Existing Debug Nets page of the Debug wizard, select Disconnect all nets and remove debug cores.

Figure 2. Removing Debug Cores in the Insertion Flow