After the nets have been marked and connected to the System ILA IP, you will need to validate the design. Validating the design ensures that all debug nets and their associated clocks are correctly connected to the System ILA.
The Validate Design command returns the following warning message:
WARNING: [BD 41-1781] Updates have been made to one or more nets/interface connections marked for debug. Debug nets, which are already connected to System ILA IP core in the block-design, will be automatically available for debug in Hardware Manager. For unconnected Debug nets, please open synthesized design and use 'Set Up Debug' wizard to insert, modify or delete Debug Cores. Failure to do so could result in critical warnings and errors in the implementation flow.
This warning message can be safely ignored if you used Designer Assistance to connect all nets marked for debug to one or more System ILA cores. Any errors returned by Validate Design should be examined and resolved.
If you have marked nets for debug that are not connected to a System ILA, use the Netlist Insertion flow to connect those signals to an ILA debug core in the top-level design. See Using the Netlist Insertion Flow for more information.
You can easily see which nets are marked for debug, and which nets are connected to the System ILA debug core by using the Layers view to display the nets, as shown in the following figure. See Displaying Layers in the Block Design for more information.
After the block design is successfully validated, you can create the HDL wrapper, and take the top-level design through synthesis and implementation. See Integrating the Block Design into a Top-Level Design.