- Open the
- On Linux, change to the directory where the Vivado tutorial design file is stored: cd <Extract_Dir>/Vivado_Tutorial. Then launch the Vivado Design Suite: Vivado.
- On Windows, launch the Vivado Design Suite: .
As an alternative, click the Vivado 2022.x Desktop icon to start the Vivado IDE.
The Vivado IDE Getting Started page contains links to open or create projects and to view documentation, as shown in the following figure:
Note: Your Vivado Design Suite installation may be called something different from Xilinx Design Tools on the Start menu.
- Under the Quick Start section, select Create Project.
- The New Project wizard opens. Click Next to confirm the project creation.
- In the Project Name page, shown in
the following figure, set the following options:
- In the Project name field, enter project_ipi.
- In the Project location field, enter <project_directory>.
- Ensure that Create project subdirectory is checked, and click Next.
- In the Project Type
page, select RTL Project, and click
Next, as shown in the following
Ensure that the Do not specify sources at this time is unchecked. If you check this box then you will not see the other options mentioned below until you get to the Default Part page.
- In the Add Sources page:
- For Target language, select VHDL or Verilog.
- For Simulator Language, select Mixed.
- Click Next.
You will add sources later using the design canvas in the Vivado IP integrator to create a subsystem design.
- In the Add Constraints page, click Next.
- In the Default Part page, shown in
the following figure, make the following entries:
- Select Parts.
- For Family, select Kintex-7.
- For Speed, select -2.
- Select xc7k325tffg900-2 part from the listed parts, and click Next.
- Review the project summary in the New Project Summary page.
- Click Finish to create the project.
The new project opens in the Vivado IDE.