With the IP subsystem design completed and validated, you need to prepare it for inclusion into the top-level HDL design. The subsystem can be included as a module or block in the top-level design, or may be the only block in the top-level design. In either case, you need to generate the HDL files for the subsystem design.
- In the Sources window, right-click
the top-level subsystem design, subsystem_1, and select Generate
This command generates the source files for the IP cores used in the subsystem design, and any related constraints file.
The Generate Output Product dialog box opens, as shown in the figure below, to regenerate the various output products associated with the subsystem design.
The Vivado IP integrator lets you choose how to handle the synthesis of the block design. The three Synthesis Options include:
- Synthesizes the block design as part of the top-level project rather than as an out-of-context block.
- Out-of-Context per IP
- Synthesizes each IP in the block design separately, out-of-context of the block design or the top-level design. This prevents each IP from being synthesized unnecessarily but requires updating and re-synthesizing each IP when it is updated.
- Out-of-context per Block Design
- Synthesizes the entire block design at one time, but out-of-context from the global or top-level design. This prevents the block design from being synthesized unnecessarily when the top-level design is synthesized but requires updating and re-synthesizing the block design when any of the IP in it are updated.
- Leave the default selection of Out of context per IP.
- Click Generate to generate all output
Alternatively, you can click Generate Block Design in the Flow Navigator, under the IP integrator drop-down menu.
The Generate Output Products dialog box opens to confirm the output products are generated.
- Click OK.
- The Out-of-context (OOC) runs for each IP in the design launch, shown in the
Design Runs window
below. OOC runs can take a few minutes to finish.
- After the Out-of-context runs are finished, in the
Sources window, right-click the
top-level subsystem design, subsystem_1,
and select Create HDL Wrapper.
The Create HDL Wrapper dialog box opens, and offers two choices:
- Copy generated wrapper to allow user edits
Choose this option if you will modify the wrapper file. Often a block design is a subset of an overall project.
In cases like these, you might need to edit the wrapper file and instantiate other design components in the wrapper. If the I/O interface of the block design changes in any manner, you must manually update the wrapper file to reflect those changes. The wrapper file created using this method is written to the <project_name>.srcs/sources_1/imports/hdl directory.
- Let Vivado manage wrapper and auto-update
- Choose this option if you want the Vivado IDE to generate and update the wrapper file as needed. The wrapper file created using this method is automatically updated every time output products for the block design are generated, to reflect the latest changes. The wrapper file is written to the <project_name>.srcs/sources_1/bd/<bd_name>/hdl directory.
- Select the default option, Let Vivado manage
wrapper and auto-update, as shown in the following figure:
- Click OK.
The Vivado IDE creates a top-level HDL wrapper for the subsystem_1 block design and adds it to the design sources.
With the top-level HDL source added to the project, you must now add design constraints to the project prior to implementation.
- From the Flow Navigator, click Add
The Add Sources wizard opens.
- Select the Add or Create Constraints option and click Next.
- In the Add or Create
Constraints page, click and select Add Files, or click the Add Files button.
The Add Constraints Files dialog box opens.
- Select top_ipi.xdc file in <Extract_Dir>, and click OK.
- In the Add or Create Constraints page, make sure that Copy constraints files into project is selected.
- Click Finish to add the constraints to the project.
You are now ready to synthesize, implement, and generate the bitstream for the top-level design.
- In the Flow Navigator, click Generate
With a single click, this will complete all the steps needed to synthesize, implement, and generate the bitstream for the design.
The No Implementation Results Available dialog box opens as seen in the following figure:
- Click Yes.
- The Launch Runs dialog box pops up where you can specify various options for launching the runs.
- Click OK.
- After the Vivado Design Suite generates
the bitstream, the Bitstream Generation
Completed dialog box opens, as shown in the following
- Click OK.
- Verify that the design meets timing by looking at the
Timing window as seen in the
Tip: The Timing Summary also reports warnings related to the lack of input and output delays for the primary input and output ports of the design. You can add these delays as design constraints using the
set_ouptut_delaycommands. See this link in the Vivado Design Suite User Guide: Using Constraints (UG903) for more information on setting input and output delays.