Step 1: Creating a New Project - 2023.2 English

To create a project, use the New Project wizard to name the project, to add RTL source files and constraints, and to specify the target device.

On Linux, do the following.

1. Go to the directory where the lab materials are stored:

   cd <Extract_Dir>/UltraScale+ (for AMD UltraScale+™ devices)

2. Launch Vivado IDE: vivado
   
   
   
   

   On Windows, do the following.

3. Launch the Vivado IDE by selecting Start > All Programs > Xilinx Design Tools > Vivado 2023.x > Vivado 2023.x (x denotes the latest version of Vivado 2023 IDE).

   As an alternative, click the Vivado 2023.x Desktop icon to start the Vivado IDE.

   The Vivado IDE Getting Started page contains links to open or create projects and to view documentation.

4. In the Getting Started page, click Create New Project to start the New Project wizard.
5. Click Next to continue to the next screen.
   
   
6. In the Project Name page, name the new project vivado_power_tutorial and enter the project location (C:\Vivado_Power_Tutorial). Make sure to check the Create project subdirectory option and click Next.
7. In the Project Type page, specify the type of project to create as RTL Project and make sure to uncheck the Do not specify sources at this time option. Click Next.
8. In the Add Sources page, do the following.
   1. Set Target Language to Verilog and Simulator language to Mixed.
   2. Click the Add Files button.
   3. In the Add Source Files dialog box, navigate to the <Extract_Dir>/UltraScale+/src directory.
   4. Select all of the Verilog (.v) source files, and click OK.
   5. In the Add Sources page, change the HDL Source For the testbench.v file to Simulation only.
      
      
   6. Verify that the files are added and Copy sources into project is checked. Click Next.
9. In the Add Constraints (optional) page, click Add Files and select dut_fpga_zcu102.xdc in the file browser. In the directory structure, the dut_fpga_zcu102.xdc file is located in the /src folder.
10. Click Next to continue.
11. In the Default Part page, click Boards and select Zynq UltraScale+ ZCU102 Evaluation Board.
    Tip: When you specify a board, you are also specifying the part you are targeting for your design, in this case an xczu9eg-ffvb1156-2-e FPGA UltraScale+ device.
12. Review the New Project Summary page. Verify that the data appears as expected, per the steps above, and click Finish.
    Note: It can take sometime for the project to initialize in the Vivado IDE.
    
    
13. In the Settings dialog box (Tools > Settings > Tool Settings > Project), enter the tutorial project directory in the Specify project directory field, so that all reports are saved in the tutorial project directory. Next, click OK.

The design is now ready for synthesis.