Scenario B

Unlike receivers based on the ZIF architecture, the RF sampling converter provides a very wide Nyquist bandwidth that allows the designer to frequency plan the blocker alias to fall outside of the wanted band. Typically, only a few ADC sampling rates are feasible with the RF sampling ADC due to the need for the ADC sample rate to be integer multiples of the 5G radio baseband rates like 30.72 MSPS. To ease this constraint, devices like the RFSoC DFE have built-in high performance, low-power fractional re-samplers to give the designer more options in frequency planning. The available conversion rates include ²/₃, ³/₄, ⁴/₅, and ⁵/₆ with more than 85 dB of anti-alias filtering performance.

Instead of setting the ADC sample rate to 2949.12 MSPS (96 x 30.72M) as in the previous scenario, a sample rate of 2211.84 MSPS can be used for the ADC to move the aliased PCS band completely outside the C-band as illustrated in the following figure.

The C band aliases to 443.68M – 723.68 MHz.
The PCS band aliases to 221.84M – 281.64 MHz.

Figure 1. Baseband Frequency Location at the ADC Output with Fs = 2211.84 MSPS

The following two figures illustrate the use of the built-in 2/3 PQ re-sampler to convert the data rate back to integer multiples of the 5G baseband rate. With this frequency plan, the blocker power can be large at the ADC input as long as it does not saturate the ADC front end. It is then removed by the highly selective digital filters in the band select DDC in the ADC core, the P/Q re-sampler, and the DFE carrier select DDC. In this design, the ADC’s full-scale input power is approximately 1 dBm, which equates to –32.4 dBm referenced at the antenna input with the AFE gain being 33.4 dB. For reference, the first 70 dB of filtering from the antenna filter is already enough for this purpose. As such, there is no consideration required for the blocker alias issue at the ADC when choosing the filter lineup. An antenna filter with 70 dB of rejection with just the AAF would be more than enough in this case. The optional BPF can be eliminated without any penalty.

Figure 2. DFE Sampling Rates at Each Stage

Figure 3. Baseband Spectrum at Each Stage of the DFE

The rich feature set of the Zynq UltraScale+ RFSoC DFE along with the fast ADC sampling speed give the radio architect many choices for handling even more complex co-location deployments. One of which is co-location with multiple interfering bands. In this case, the designer has the option to:

Frequency plan all blocker bands to alias outside of the wanted band.
If this is not feasible, the designer can prioritize bands that would impact the filter design the most (such as co-locating bands closer to the wanted band).

The flexibility and high performance of the Zynq UltraScale+ RFSoC DFE device together with the readily available low cost, small footprint chip filters render the co-location requirements rather trivial. There are no additional burdens on the antenna filter to handle this versus the non-co-location scenarios regardless of ADC architecture design.