Test bench TB_HW_ZUP is available as part of the reference design. The test bench TB_HW_ZUP is designed for the ZCU102 demonstration board. This test bench can be implemented to show the NIDRU data recovery capability with both synchronous and asynchronous inputs.
To compile the test benches, source the script nidru_design_zup.tcl from the Vivado Design Suite. The test bench architecture is shown in This Figure.
The test bench includes:
•Two STM1/OC3 receivers, based on NIDRU, operating on a 125 MHz reference clock.
•Two Fast Ethernet receivers, based on NIDRU, operating on a 155.52 MHz reference clock.
Channel 0 transmits data synchronized with REFCLK 125 MHz, while Channel 1 transmits data synchronized with REFCLK 155.52 MHz. The GTHE4 Channels are cross connected via a SFP cable so that each receiver receives data at a frequency not synchronized to its own reference clock.
The two reference clocks are generated on board by using the system controller. The reference clock frequencies are configured through the serial interface on the ZCU102 board.
In each Quad, only two SerDes are used.
Each of the two channels is equipped with:
•A PRBS generator continuously sending a PRBS 7 or PRBS 31 pattern. The user can force each of the two PRBS generators to generate an error using the Vivado Logic Analyzer to show error detection on the corresponding PRBS checker.
•A PRBS checker continuously checking the incoming PRBS 7 or PRBS 31 pattern. The ERR output indicates detection of at least one error from the last ERR_RST. ERR is connected to the virtual input/output (VIO) and checked in real time. An error counter is also provided.
The specific PRBS pattern used in this application note for both the generator and the checker is based on the polynomial x31 + x28 + 1 for PRBS 31, x7 + x6 + 1 for PRBS 7 and can be changed to any other industry standard PRBS type.
Each PRBS checker works on the data delivered by the barrel shifter, which is instantiated right after each NIDRU block. This Figure reports the detailed description of all signals of the test bench which are controlled by the Vivado Logic Analyzer.
Both the 125 and 155 blocks are controlled in the same way, but with a different VIO. The pin names are consistent across the VHDL code, the logic analyzer project, and this application note.
Each transmitter has the option to be set to generate a PRBS pattern, as described previously, or to synthesize a recovered clock. This mode, which can be activated on the fly, allows showing the capability of NIDRU to synthesize the recovered clock.
When the application works properly, all LEDs are green.
In case of an error in the datapath, the corresponding LEDs (highlighted with dashes in This Figure) for the signals chk_okko_gt0 and/or chk_okko_gt1 are red.
The example design needs two asynchronous and independent clocks (155.52 MHz and 125 MHz). The ZCU102 board can provide two different clocks through the system controller. In the example design supplied with this application note, the system controller can be programmed by the System Controller User Interface and using the serial interface on the ZCU102 board.
The System Controller GUI software rdf0382-zcu102-system-controller-c-2019-1 can be downloaded from the ZCU102 Product Page [Ref 3].
This Figure shows the setup to generate the correct frequencies of 125 MHz and 155.52 MHz.
To test the eye-scan feature, configure the ILA Capture Mode Settings and Trigger Mode Settings as shown in the This Figure.
The trigger is done on the rising edge of the signal EN_ERR_COUNT_0 asserting the signal START_EYESCAN available in the VIO window.