Clock and Data Recovery Unit based on Deserialized Oversampled Data (XAPP1240)

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3.1 English

This application note is divided into four sections:

NIDRU Block Diagram and Pinout
Describes the structure of the NIDRU wrapper and its pinout.

NIDRU Usage Model
Describes how to configure the NIDRU ports and attributes.

Simulating the NIDRU
Describes the test bench used to simulate the DRU.

FPGA Hardware Test Bench
Describes the TB_HW_DRU test bench, available in the reference design.

The Fast Ethernet case (125 Mb/s ± 100 ppm) and OC3/STM1 (155.520 Mb/s ± 20 ppm) are used as practical examples throughout the application note.