This section describes the usage model and how to configure the NIDRU ports and attributes based on the user application requirements. The usage model describes how to algorithmically size the hardware parameters G1, G2, G1_P, and CENTER_F.
The general clocking structure around the NIDRU is shown in This Figure. Two clock domains are highlighted, remote and local. The frequency is indicated in brackets for each clock domain.
IMPORTANT: The NIDRU clock is always locked to the PHY clock, and is thus part of the same clocking domain. In most cases, the ratio between the two clocks is 1.
This Figure is a high-level diagram where the divide/multiply function is typically performed internally in the SerDes block, by a PLL, or by a general interconnect divider in conjunction with the EN signal of the NIDRU.
EN_OUT is synchronized to the local clock. However, the rate at which EN_OUT is set to 1 by the NIDRU is locked to the remote clock domain, filtered by the phase transfer function performed by the NIDRU.
The key feature of the NIDRU is that the ratio between the remote clock domain and the local clock domain can be fractional, and this ratio is specified using CENTER_F.