PHY Configuration

Clock and Data Recovery Unit based on Deserialized Oversampled Data (XAPP1240)

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3.1 English

This section provides recommendations for correctly configuring the PHY.

The NIDRU processes oversampled data from a PHY, which is usually a SelectIO interface or a SerDes. In the case of a SerDes, it has to be configured in lock to reference mode, and its auto-adapting equalizer should be disabled by setting these ports to the values listed here:






These ports are available in the test bench through VIO. The following section describes configuring the GTH transceiver using the UltraScale FPGA Transceiver Wizard in the IP Catalog.


RECOMMENDED:   Download the most recent version of the IP core before using the wizard. For details on how to use this wizard, see the UltraScale FPGAs Transceivers Wizard: LogiCORE IP Product Guide 
(PG182) [Ref 5].

Configure the Basic tab as shown in This Figure. Set the receiver line rate at the oversampling rate. In the example, the line rate is set to 2.5 Gb/s which is 20 times the Fast Ethernet rate. The transmitter can be used to synthesize the recovered clock by setting it at the same rate as the receiver.

Figure 15:      Configuration of the Basic Tab

X-Ref Target - Figure 15


Under the Structural Options tab, check all the ports that are highlighted in This Figure and This Figure to expose them in the generated wrapper. All of the ports chosen to be exposed must be set to 1.

Figure 16:      Ports to be Exposed in the Structural Options Tab

X-Ref Target - Figure 16

Figure 17:      Additional Ports to be Exposed in the Structural Options Tab

X-Ref Target - Figure 17