Reference Design

General

Developer name

Paolo Novellini, Antonello Di Fresco, and
Giovanni Guasti

Target devices

7 series, UltraScale, UltraScale+, and Versal devices

Source code provided

Yes, partially encrypted

Source code format

VHDL

Design uses code and IP from existing Xilinx application notes and reference designs or third-party sources

This reference design uses code from the application note An Attribute-Programmable PRBS Generator and Checker (XAPP884) [Ref 4].

Simulation

Functional simulation performed

Yes

Timing simulation performed

N/A

Test bench used for functional and timing simulations

Yes

Test bench format

VHDL

Simulator software/version used

ModelSim 10.6b

SPICE/IBIS simulations

N/A

Implementation

Synthesis software tools/versions used

Vivado synthesis

Implementation software tools/versions used

Vivado implementation

Static timing analysis performed

Yes

Hardware Verification

Hardware verified

Yes

Hardware used for verification

ZCU102 board with Zynq UltraScale+ MPSoC