The purpose of the TB_SIM_DRU_JITTER test bench is to simulate the ability of the NIDRU to operate at several popular data rates with synchronous and plesiochronous serial inputs. The simulation covers the six cases shown in Table: Simulation cases in sequence. The user application data rate can be added as an additional case.
Case 2 and case 4 show the ability of NIDRU to work at both fractional and integer oversampling rates. Case 6 shows the ability of the NIDRU to operate even at very low data rates, even 1 Kb/s, equivalent to a 125K oversampling rate.
To run the simulation script:
1.Open a DOS command window.
2.Change to the scripts directory.
4.In ModelSim, run the script run_sim_do.
IMPORTANT: Although the test bench has been tested with Modelsim only, the NIDRU core is also expected to operate with these simulation tools: Vivado® simulator, Mentor Graphics Modelsim, and Synopsys VCS.
The architecture implemented in the TB_SIM_DRU_JITTER test bench is shown in This Figure. An ideal deserializer and serializer are used instead of a full SerDes to minimize the simulation time. The serializer and deserializer datapath is 20 bits or 32 bits, programmable through the DTIN_WIDTH attribute.
The test bench contains two clock domains:
•The clock domain of the line, synchronized to CLK_DT
•The clock domain of the DRU, synchronized to REFCLK and to HF_CLK
The pseudo-random binary sequence (PRBS) generator works at full speed on CLK_DT and can generate any kind of industry standard PRBS [Ref 4]. The ideal deserializer, the NIDRU, and the PRBS checker all work on the local REFCLK domain.
During test case 1, a 1 ns step in the input datastream is applied (see This Figure). The purpose of this is to show the ability of the NIDRU to respond exponentially to an input phase step.
During test case 2 and case 5, the eye scan is plot with PH_NUM = 1 (see This Figure).
An example of eye scan with two phases (PH_NUM = 2) is shown in This Figure.