There are a few basic hardware requirements for implementing an encrypted design flow:
• For programming ability and debugging capability: A JTAG connection to the FPGA.
• For BBRAM key storage: Battery to V BATT (see the respective data sheet for battery voltage requirements).
• For eFUSE key storage: V BATT or V CCAUX is recommended to enable the ability to test with BBRAM flow prior to burning the one-time programmable (OTP) eFUSEs.