Revision History

Using Encryption and Authentication to Secure an UltraScale/UltraScale+ FPGA Bitstream Application Note (XAPP1267)

Document ID
XAPP1267
Release Date
2023-02-10
Revision
1.6 English

The following table shows the revision history for this document.

Date

Version

Revision

02/10/2023

1.6

Updated description for Bits[0:2, 6] in Table: eFUSE Control Register Bit (FUSE_CNTL) Description

Cleaned up Encryption settings code in Creating an Encryption Key and Encrypted Bitstream

Added Table: Vector Size

03/16/2022

1.5

Added security issue description in Summary

Added Design Advisory 76171 in Key Rolling

Updated and added recommended notes in Creating an Encryption Key and Encrypted Bitstream

Added 96 bits description to BITSTREAM.ENCRYPTION.STARTIV0 and BITSTREAM.ENCRYPTION.STARTIVOBFUSCATE in Table: Write_bitstream Properties

03/26/2021

1.4

Updated FUSE_RSA and FUSE_KEY contents and descriptions in Table: eFUSE Register Description

Updated Table: eFUSE Control Register Bit (FUSE_CNTL) Description

Updated bits 0-2 in Table: eFUSE Control Register Bit (FUSE_SEC) Description

Added recommended note and coding in Creating an Encryption Key and Encrypted Bitstream

Updated Possible Value for BITSTREAM.ENCRYPTION.RSAKEYLIFEFRAMES in Table: Write_bitstream Properties

Updated This Figure

Updated Fallback and IPROG description in Loading the Encrypted Bitstream

10/12/2018

1.3

Clarified Obfuscated Keys . Changed BITSTREAM.ENCRYPTION.STARTIV0 hex value from 32 bits to 128 bits in Table: Write_bitstream Properties and in line 14 in the file code snippet. Added content to line 16 in the file code snippet. Clarified eFUSE programming solutions bulleted list under Loading the Encryption Key . Replaced [Ref 7] under References .

08/15/2018

1.2

Updated eFUSE register descriptions in Table: eFUSE Register Description . Clarified R_DIS_Key description (bit 0) and ad ded W_DIS_USER_128 (bit 16) in Table: eFUSE Control Register Bit (FUSE_CNTL) Description . Added FUSE_BKS_ENAB (bit 6) and reserved bits 7-31 in Table: eFUSE Control Register Bit (FUSE_SEC) Description . Clarified write_bitstream properties in Table: Write_bitstream Properties . Added eFUSE Programming General Recommendations .

04/13/2017

1.1

Added reference to Design Advisory 68832 under Summary .

06/02/2016

1.0

Initial Xilinx release