This block diagram inserts a Xilinx DMA PCIe IP core with two AXI4-Stream receive channels and one AXI4-Stream transmit channel. Any number of AXI4-Stream channels can be turned on. However, one of the receive channels must be used to receive the bitstream from the PCIe host, and then transfer that bitstream to the ICAP. In this case, channel 1 is the designated receive channel for the ICAP. In this example, channel 0 receive is looped around to channel 0 transmit, but a real application would have these channels interfacing to the user logic.
The DMA channel 1 path goes to an asynchronous FIFO to make it easy to cross clock domains from the PCIe domain to the ICAP domain. The maximum frequency of the ICAP clock domain will depend on the device selected, and it can be found in the device data sheet.
From the domain crossing FIFO, the AXI4-Stream goes to an AXI4-Stream data width converter. The size of the AXI4-Stream path from the DMA interface will be dependent on the PCIe link width and speed. The ICAP width is fixed at 32 bits for all devices.
Integrated Logic Analyzer (ILA) cores have been inserted throughout the data path to be able to monitor activity during operation. These ILAs can be removed and are not necessary for normal operation.