Compile the Reference Design

In the Flow Navigator, click Run Implementation to pull the design all the way through place and route, which will:

Run synthesis of all IP and sub-modules
Implement the parent configuration
Implement the child configuration using the Partial Reconfiguration project flow

When implementation completes, a dialog box opens. Click Cancel (or Open Implemented Design).

Note: Do not run bitstream generation here, because the design properties are not set up for flash programming of the full bitstream or PCIe-based delivery of the partial bitstreams. Different options are required for each and this scenario is not yet supported within Vivado project mode.

In the Tcl Console, to create all full and partial bit files, source this script:

source create_all_bitstreams.tcl

This creates the full device bitstream (with compression enabled) for the parent configuration with the required options for dual QSPI programming:

CONFIG_MODE: SPIx8
SPI_BUSWIDTH: 8
CONFIGRATE: 51.0

The script will also generate partial bitstreams for the shift_right and shift_left Reconfigurable Modules with the required CONFIG_MODE of S_SELECTMAP32 needed for the ICAP. Bitstream compression is disabled to ensure consistent sizes for all partial bit files.

With these three bitstreams created and placed in the Bitstreams folder, the final step is to generate:

.mcs files for dual QSPI flash programming
.bin files for partial reconfiguration programming over PCIe

In the Tcl Console, to create all the required programming files, source this script:

source create_bin_and_prom.tcl

This formats each partial bitstream for 32-bit SelectMAP delivery, and formats the full device bitstream for dual QSPI configuration.