This Partial Reconfiguration project has been created with the Vivado® 2018.1 integrated design environment (IDE) and validated with the Vivado 2018.3 IDE. Two versions are available — the same basic design can target either the VCU118 or KCU116 development platforms. The only differences between the two versions are physical constraints (such as pin locations and Pblocks) and the frequency of clock driving the ICAP. While created specifically for UltraScale+™ devices, the same concepts can be applied to UltraScale™ devices. The only difference is the requirement for delivering clearing bitstreams for UltraScale prior to loading the next partial bitstream.
The design archives contain the base design ready for compilation in the Vivado IDE. Bitstreams and dual QSPI flash images are available in the Bitstreams_VCU118 and Bitstreams_KCU116 folders for immediate hardware testing. Please remember that any newly compiled version will create full and partial bitstreams that are incompatible with the bitstreams supplied in this design archive — always keep bitstream versions in sync.
Download the reference design files for this application note from the Xilinx® website.