Download the reference design files for this application note from the Xilinx website.
Reference Design Matrix
The following checklist indicates the procedures used for the provided reference design.
| Parameter | Description |
|---|---|
| General | |
| Developer name | Xilinx |
| Target devices | Zynq Zynq UltraScale+ MPSoCs |
| Source code provided? | Y |
| Source code format (if provided) | C |
| Design uses code or IP from existing reference design, application note, third party or Vivado® software? If yes, list. | N/A |
| Simulation | |
| Functional simulation performed | N |
| Timing simulation performed? | N |
| Test bench provided for functional and timing simulation? | N |
| Test bench format | N/A |
| Simulator software and version | N/A |
| SPICE/IBIS simulations | N |
| Implementation | |
| Synthesis software tools/versions used | N/A |
| Implementation software tool(s) and version | N/A |
| Static timing analysis performed? | N |
| Hardware Verification | |
| Hardware verified? | Y |
| Platform used for verification | ZCU102 |