The following figure shows a summary of the reference design flow.
Figure 1. Reference Design Flow
- Create an FSBL for the Arm Cortex-A53 Core
- Modify BSP to Include XilSkey Library
- Create a Lab Application for the Arm Cortex-A53 based APU
Download and Run Lab Application
Program the PPK0 and PPK1 Digest eFUSEs
- Forcing RSA Authentication
- Verification of Device Provisioning
- Generating a Secure Boot Image and Booting the Secured ZCU102 Device
Zynq UltraScale+ Standard Key Revocation