Algorithm Illustration

Synchronization of Signal Processing in Multiple RF Data Converter Subsystems (XAPP1349)

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1.0 English

For any RFSoC, MTS will send the rising edge of analog_sysref across the FIFO from the ADC tile to PL or vice versa for the DAC. A counter stops once this rising edge is detected in PL. This counter is reset by each rising edge of the PL_sysref in PL and incremented by each word from FIFO. Once the counter stops, the counter value represents the relative propagation latency of this FIFO. Running the same measurement for all selected tiles in the device, MTS gets the FIFO mismatch of all tiles and then aligns them by adding additional delays to ensure that the delay through each FIFO matches the largest measured delay. When the system contains several RFSoCs, the system just needs to call the MTS function for each device.

Users should note that the measured FIFO latency is a relative value and not representative of the physical propagation delay across FIFO, because the measured delay is depending on when the counter is reset with reference to the rising edge of analog_sysref.