The Zynq UltraScale+ RFSoC achieves high accuracy synchronization across multiple channels and chips via MTS.
In comparison with the JESD-204B/C standard, the MTS benefits from the integration of converters and FPGA in one chip, which gives the alignment accuracy tolerance significant better than ±T1 (± one converter sampling clock period) without complex 204B/C transceiver and synchronizing process. The MTS also supports deterministic latency with relaxed clock scheme in the system using a single API call.
It is possible to achieve significantly better alignment than ±T1 by optimizing system design including board design. Refer to UltraScale Architecture PCB Design User Guide (UG583) for specific board design recommendations. The following sections detail the various design aspects to which users should pay close attention to achieve optimized synchronization performance.
Synchronization of a system using multiple RFDC sub-systems with one or several devices requires a common clock synchronization through the set of sub-systems. Where several synthesizers are used to supply the reference clock to the RFDC, clock synchronization is mandatory, otherwise the random frequency drift from the different sources will be unpredictable. Sampling clocks from different PLLs are acceptable, but these PLLs must be frequency locked and phased aligned.
When frequency drift among a set of clocks of RFDC subsystem is no longer a concern, the MTS feature of Zynq UltraScale+ RFSoC will handle alignment of the propagation delay from converters to the programmable logic and vice versa. MTS aligns all synchronous blocks within the tiles, then aligns the dual clock FIFO interface between the PL and RFDC through pointer adjustments.
In addition to the sampling clocks used in RFDC subsystem clock domains and PL clocks used in PL domains, the MTS also relies on time base references analog_sysref (tied to RFDC clock domains) and PL_sysref (tied to PL clock domain) to perform alignment. These low jitter signals are used to measure propagation delay from a common and precise time reference in the 2 different clock domains. They are also used to trigger sub-system events linked to phase alignment requirements.
In summary, the MTS algorithm achieves alignments across multiple RFDC subsystems from one or more RFSoCs using a measure and adjust mechanism. The measure and adjust mechanism relies on the analog_sysref and PL_sysref timing reference. As an example, the following figure shows an overview of the MTS across two chips.
There are 2 RFSoCs and one ADC channel for each chip illustrated in Figure 1, however, there are up to 16 ADCs and 16 DACs in a single chip. There is no limitation to number of RFSoCs or converter tiles from the MTS mechanism, the similar architecture can be expanded to include more RFSoC chips in the system.