We go through the potential sources in a system which impact the synchronization across RF channels using different clocking system to sample data. The following summary gives some notes for optimized alignment across multiple chips:
- There are four key clocks groups: sample clock group (RF-ADCs and RF-DACs), PL_clock group, analog_sysref group and PL_sysref group; the clocks should be well aligned each other’s within their clock groups.
- The phase relationship between these four groups must be fixed over reset to reset cycles to ensure determinism.
Comparing with the JESD-204B/C interface, the sampling clock and PL_clock groups are similar to the device clocks group, and the PL_sysref and analog_sysref groups are like the sysref group, although the requirements are easier to meet with the Zynq UltraScale+ RFSoC compared to JESD-204B/C.
- Clock PCB trace mismatches introduce misalignment directly on RF paths and misalignment can be corrected by MTS algorithm in most of the cases. To align the length of traces on above key clock signals is a good practice to achieve the optimized synchronization.
- Using well aligned external sampling clock directly instead of multiple on-chip RF PLLs will achieve better alignment performance
- The skew of external clock generator and clock buffer need to be considered for the best MTS accuracy performance.
The above are general requirements for most multiple channel system who need synchronization.
Finally, the on-chip clock distribution network reduces the number of external clock routing and helps to align these clock traces inside the chip. This use of the on-chip clock forwarding can give the best trace alignments between channels tile usage when well balanced, see Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) for application details of clock forwarding in the third generation of Zynq UltraScale+ RFSoC. The higher channel density the chip will get, the smaller number of clocks on board need to meet strict constraints.