Deterministic Latency

Synchronization of Signal Processing in Multiple RF Data Converter Subsystems (XAPP1349)

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1.0 English

The latency determinism requires a fixed delay across channels and chips over reset to reset cycles.

The Zynq UltraScale+ RFSoC supports this feature by applying MTS with a targeted delay which is simply an optional user parameter of the MTS algorithm. This targeted latency value is expressed in a multiple of T1 and can be extracted by MTS process report itself. It should then be applied with a small margin as explained in the Zynq UltraScale+ RFSoC product guide. The main principle here is to force the algorithm with a fixed delay target which the system can achieve in the MTS process.

To achieve strict deterministic latency over multiple chips, as mentioned in Dual Clock FIFO section, the analog_sysref and PL_clock signal groups must keep constant phase relationship over reset to reset cycles.