The FIFOs are located between the RF converters (Analog converters together with RF Datapath) and the PL to buffer data and transfer between the PL and RFDC clock domains. Because the read and write clocks are from different clock domains, these clocks can have a different phase relationship over power on/off cycles. We must distinguish between the RFDC clock domain and the PL clock domain.
The following figure shows how MTS evaluates the misalignment between FIFOs. The ADC channel is used as example and similar operation is performed for DAC with the opposite signal flow direction.
The propagation delay between FIFOs is uncertain after initialization, this is normal for most dual clock FIFOs. The MTS mechanism measures the propagation delay of each FIFO and compensates for the difference between them. This operation will not only align all FIFO delays, but also ensures deterministic latency across FIFOs over multiple power cycles if users apply a specific latency value with margin as explained in Zynq UltraScale+ RFSoC product guide. The resolution of this compensation is one sampling clock period (T1).
By using the FIFO measurement and compensation procedure we know that the absolute alignment between each of these clock groups (analog_sysref, PL_sysref, PL_clock and sample clock) are not critical, while the alignment within each clock groups are critical for synchronization across multiple tiles or chips:
- Alignment of all PL_sysref across chips
- Alignment of all analog_sysref across chips
- Alignment of all sampling clock across chips
- Alignment of all PL clock across chips
Board design should make sure the clock source is stable to keep a constant phase relationship between them over time, this makes sure a safe and stable capturing of analog_sysref and PL_sysref by sample clock and PL_clock respectively. When MTS is used on a single chip, there are no PCB trace alignment constraints on these four key signals used to manage timing references. But the constant phase relationship within each clock domain is still necessary.
For strict deterministic latency over reset to reset cycles, the following requirement must be met:
- Constant phase relationship between analog_sysref and PL_sysref supplied to the device over reset to reset cycles.