Multi-channel applications targeting very large scale systems (RADAR, electronic warfare, satellite communication, and massive MIMO) are now combining multiple input multiple output (MIMO), beam-forming, and controlled latencies with other classical requirements of RF channel design such as linearity, noise and spectral purity. This shift in technology is occurring simultaneously to the move to the RF direct conversion to enable the level of integration required. The radio transmitter and radio receiver architecture, a MIMO system will trigger a requirement to distinguish multiple data streams, the following figure illustrates a typical MIMO system in which the channel alignment is critical.
Most of the technologies used to encode and decode the information are passing through the radio signal requires RF path alignment to enable the MIMO transceiver system. This requirement becomes mandatory and critical when the RF subsystem enables beam-forming. Therefore, latency control from user data to the antenna becomes a critical requirement and is linked to the design system RF clocking requirements using direct RF conversion. The application may have different requirements:
- The latency alignment– The difference in latency between channels.
- The latency determinism– The total latency for each channel is consistent between start-ups of the full system.
The following figure illustrates the concepts of latency alignment and latency determinism.
In any systems with multiple independent RF converters and clocking structures, there are several potential sources of latency uncertainty. Matching these latencies is critical, but also challenging and can consume a lot of power in a large system using multiple discrete converters. Discrete converters have standardized the use of the JESD204B SYSREF scheme for synchronization. Similarly, the Zynq® UltraScale+™ RFSoC has implemented a complementary, simplified scheme using SYSREF signal, which is a shared signal that defines a common timing reference.
The integration of the RF data converters in the Zynq UltraScale+ RFSoC results in the elimination of the serial transceiver links for RF digital communication that typically consume power and add latency. However, to provide a flexible clocking and number of data words for the PL (Programmable Logic) design, each RF-ADC and RF-DAC digital signal processing block incorporates independent gearbox FIFOs. These FIFOs allow data to be transferred between the PL clock domain and the RF converter sample clock domain which can result in a non-deterministic latency across the async FIFO, which causes the uncertainty in latency between different tiles. This latency is measured and corrected using the Multi-Tile Synchronization (MTS) feature.