MTS Results

Synchronization of Signal Processing in Multiple RF Data Converter Subsystems (XAPP1349)

Document ID
Release Date
1.0 English

The phase difference of each tile versus reference tile (tile 0 used in this measurement) has been measured under the combination of different temperatures, voltage supplies, manufacturing process corners and clock scheme. Measurements showed excellent alignment across multiple tiles on ZU49DR, and the alignment is almost independent over temperature and voltage, and also proved that sampling clock distribution is better than reference clock distribution as we mentioned in previous section. For the tests clock forwarding feature was used to distribute either the external sampling clock (0-PLL), internal PLL RF sampling clock(1-PLL) or the internal PLL reference clock to multiple PLLs (4-PLLs). Figure 1 gives an example, refer to the characterization report for detailed results.

Figure 1. ADC MTS Min/Max Values

Figure 1 gives the minimum and maximum alignments of RF-ADC tiles in lab measurements, over different clock distribution schemes and temperatures. Measurement showed the alignment varies little over temperature from -40 to 110 degrees. the 4-PLL clock scheme (reference clock forwarding to each tile and generate sample clock by in-tile PLLs) showed the biggest spread over 0-PLL (distribute external sample clock) and 1-PLL (distribute sample clock generated by one in-tile PLL) clock schemes. Results also demonstrate that there is very little difference in MTS alignment performance between using the distributed internal PLL and the distributed external RF sampling clock.

The following figure shows similar measurement results of RF-DAC tiles.

Figure 2. DAC MTS Min/Max values