Misalignment in Programmable Logic

Synchronization of Signal Processing in Multiple RF Data Converter Subsystems (XAPP1349)

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PL_clock and PL_sysref are the key clocks in FPGA side for synchronization.

The following figure shows a brief implementation of MTS related clocks in programmable logic.

Figure 1. MTS Related Clocks in Programmable Logic

The PL SYSREF must be sampled by the PL clock to make it synchronous to the PL clock domain. We can consider the PL SYSREF and the User SYSREF to be conceptually the same. This doesn't affect the measurement theory outlined above.

In most real applications, the clock used in PL domain to interface with RFDC dual clock FIFO is different from the PL_clock. Hence MMCM in PL domain is used to synthesize the wanted PL_clock driving the FIFO clocks for interfacing RFDC sub-system.

As indicated in Zynq UltraScale+ RFSoC RFDC product guide [Ref 1] the FIFO clock rates of both ADC and DAC must be common multiple of PL_sysref and PL_Clock. For synchronization across multiple chips, an additional requirement is MMCM use to drive FIFO clock must enable external 0-delay mode, this helps to align the FIFO clocks across multiple chips.

For example, if the desired FIFO clocks are 300MHz in a system multiple MMCM will generate phase aligned outputs from a PL_clock of 100MHz, but may generate misaligned 300MHz when the PL_clock is 200MHz. MTS is not aware of this misalignment.