where:
- c is the velocity of electromagnetic field in vacuum.
- Er is the relative dielectric constant of PCB material.
The following figure illustrates the trace mismatch in the signal path.
For example, on a PCB with the relative dielectric constant of 4, assuming the mismatch of two traces is 100mil, the misalignment in time is around 16.9ps, for the carrier frequency of 3.5GHz, which lead to a misalignment of 21.35° in degree.
If the digital up/down conversion is enabled in the data path, the misalignment in degree doesn't change and the Δt should be calculated based on the Δϕ (radian difference) of IF (intermediate frequency). This can be derived from the following formula (down conversion for example):
Where the Δϕ is the misalignment in radians at carrier frequency.
Trace mismatch must be controlled by the PCB designer because MTS can only provides digital alignment in the tile and programmable logic. Trace length compensation to achieve the best possible alignment at the system level must be handled primarily by the PCB design. There is scope to calibrate out any residual alignment in channel using DSP blocks in the Programmable Logic.